IMAQ FPGA Extract VI
- Updated2023-02-21
- 42 minute(s) read
Requires: NI Vision Development Module FPGA
Extracts (reduces) an image or part of an image with adjustment of the horizontal and vertical resolution.
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Note
This VI has variable latency, which is dependent on the image size. Plug the Minimum Latency value from the Estimated Performance section into the following formula to determine the total latency. The left and top values are parameters that should be supplied when the Optional Rectangle is used. If Optional Rectangle is not used or the extract is performed on the entire image, the left and top values are 0. For the x1 VI instances, use this formula to calculate the total latency.
For the x8 VI instances, use this formula to calculate the total latency.
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IMAQ FPGA Extract U1x1
Extracts (reduces) an image or part of an image with adjustment of the horizontal and vertical resolution.
Supported Image Types

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Optional Rectangle defines a four-element array that contains the left, top, right, and bottom coordinates of the region to process. The right and bottom values are exclusive and lie outside the region. The VI applies the operation to the entire image if Optional Rectangle is empty or not connected. |
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Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
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Xstep is the vertical sampling step, which defines the columns to be extracted (the horizontal reduction ratio). For example, with an Xstep equal to 3, one out of every three columns is extracted from the Pixel Bus In into the Pixel Bus Out. Each column is extracted if the default value (1) is used. |
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Y Step Size is the horizontal sampling step, which defines the lines to be extracted (the vertical reduction ratio). Each row is extracted if the default value (1) is used. |
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Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
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Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
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Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
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![]() |
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
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IMAQ FPGA Extract U1x1 Details
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Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 482
- Slice LUTs: 546
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 2
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 451
- Slice LUTs: 532
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 2
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 103
- Slice LUTs: 175
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 3
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 452
- Slice LUTs: 365
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Extract U1x8
Extracts (reduces) an image or part of an image with adjustment of the horizontal and vertical resolution.
Supported Image Types

![]() |
Optional Rectangle defines a four-element array that contains the left, top, right, and bottom coordinates of the region to process. The right and bottom values are exclusive and lie outside the region. The VI applies the operation to the entire image if Optional Rectangle is empty or not connected. |
||||||||||
![]() |
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
![]() |
Xstep is the vertical sampling step, which defines the columns to be extracted (the horizontal reduction ratio). For example, with an Xstep equal to 3, one out of every three columns is extracted from the Pixel Bus In into the Pixel Bus Out. Each column is extracted if the default value (1) is used. |
||||||||||
![]() |
Y Step Size is the horizontal sampling step, which defines the lines to be extracted (the vertical reduction ratio). Each row is extracted if the default value (1) is used. |
||||||||||
![]() |
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
![]() |
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
![]() |
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
![]() |
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
![]() |
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Extract U1x8 Details
![]() |
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 1170
- Slice LUTs: 2228
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 10
- Initiation Interval: 1
IMAQ FPGA Extract U8x1
Extracts (reduces) an image or part of an image with adjustment of the horizontal and vertical resolution.
Supported Image Types

![]() |
Optional Rectangle defines a four-element array that contains the left, top, right, and bottom coordinates of the region to process. The right and bottom values are exclusive and lie outside the region. The VI applies the operation to the entire image if Optional Rectangle is empty or not connected. |
||||||||||
![]() |
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
![]() |
Xstep is the vertical sampling step, which defines the columns to be extracted (the horizontal reduction ratio). For example, with an Xstep equal to 3, one out of every three columns is extracted from the Pixel Bus In into the Pixel Bus Out. Each column is extracted if the default value (1) is used. |
||||||||||
![]() |
Y Step Size is the horizontal sampling step, which defines the lines to be extracted (the vertical reduction ratio). Each row is extracted if the default value (1) is used. |
||||||||||
![]() |
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
![]() |
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
![]() |
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
![]() |
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
![]() |
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Extract U8x1 Details
![]() |
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 485
- Slice LUTs: 553
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 2
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 455
- Slice LUTs: 526
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 2
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 156
- Slice LUTs: 208
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 3
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 504
- Slice LUTs: 399
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Extract U8x8
Extracts (reduces) an image or part of an image with adjustment of the horizontal and vertical resolution.
Supported Image Types

![]() |
Optional Rectangle defines a four-element array that contains the left, top, right, and bottom coordinates of the region to process. The right and bottom values are exclusive and lie outside the region. The VI applies the operation to the entire image if Optional Rectangle is empty or not connected. |
||||||||||
![]() |
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
![]() |
Xstep is the vertical sampling step, which defines the columns to be extracted (the horizontal reduction ratio). For example, with an Xstep equal to 3, one out of every three columns is extracted from the Pixel Bus In into the Pixel Bus Out. Each column is extracted if the default value (1) is used. |
||||||||||
![]() |
Y Step Size is the horizontal sampling step, which defines the lines to be extracted (the vertical reduction ratio). Each row is extracted if the default value (1) is used. |
||||||||||
![]() |
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
![]() |
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
![]() |
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
![]() |
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
![]() |
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Extract U8x8 Details
![]() |
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 2511
- Slice LUTs: 5045
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 10
- Initiation Interval: 1
IMAQ FPGA Extract U16x1
Extracts (reduces) an image or part of an image with adjustment of the horizontal and vertical resolution.
Supported Image Types

![]() |
Optional Rectangle defines a four-element array that contains the left, top, right, and bottom coordinates of the region to process. The right and bottom values are exclusive and lie outside the region. The VI applies the operation to the entire image if Optional Rectangle is empty or not connected. |
||||||||||
![]() |
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
![]() |
Xstep is the vertical sampling step, which defines the columns to be extracted (the horizontal reduction ratio). For example, with an Xstep equal to 3, one out of every three columns is extracted from the Pixel Bus In into the Pixel Bus Out. Each column is extracted if the default value (1) is used. |
||||||||||
![]() |
Y Step Size is the horizontal sampling step, which defines the lines to be extracted (the vertical reduction ratio). Each row is extracted if the default value (1) is used. |
||||||||||
![]() |
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
![]() |
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
![]() |
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
![]() |
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
![]() |
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Extract U16x1 Details
![]() |
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 535
- Slice LUTs: 622
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 2
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 505
- Slice LUTs: 561
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 2
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 41
- Slice LUTs: 46
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 3
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 564
- Slice LUTs: 443
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Extract U16x8
Extracts (reduces) an image or part of an image with adjustment of the horizontal and vertical resolution.
Supported Image Types

![]() |
Optional Rectangle defines a four-element array that contains the left, top, right, and bottom coordinates of the region to process. The right and bottom values are exclusive and lie outside the region. The VI applies the operation to the entire image if Optional Rectangle is empty or not connected. |
||||||||||
![]() |
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
![]() |
Xstep is the vertical sampling step, which defines the columns to be extracted (the horizontal reduction ratio). For example, with an Xstep equal to 3, one out of every three columns is extracted from the Pixel Bus In into the Pixel Bus Out. Each column is extracted if the default value (1) is used. |
||||||||||
![]() |
Y Step Size is the horizontal sampling step, which defines the lines to be extracted (the vertical reduction ratio). Each row is extracted if the default value (1) is used. |
||||||||||
![]() |
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
![]() |
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
![]() |
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
![]() |
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
![]() |
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Extract U16x8 Details
![]() |
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 4045
- Slice LUTs: 7786
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 10
- Initiation Interval: 1
IMAQ FPGA Extract RGB32x1
Extracts (reduces) an image or part of an image with adjustment of the horizontal and vertical resolution.
Supported Image Types

![]() |
Optional Rectangle defines a four-element array that contains the left, top, right, and bottom coordinates of the region to process. The right and bottom values are exclusive and lie outside the region. The VI applies the operation to the entire image if Optional Rectangle is empty or not connected. |
||||||||||||||||||
![]() |
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
![]() |
Xstep is the vertical sampling step, which defines the columns to be extracted (the horizontal reduction ratio). For example, with an Xstep equal to 3, one out of every three columns is extracted from the Pixel Bus In into the Pixel Bus Out. Each column is extracted if the default value (1) is used. |
||||||||||||||||||
![]() |
Y Step Size is the horizontal sampling step, which defines the lines to be extracted (the vertical reduction ratio). Each row is extracted if the default value (1) is used. |
||||||||||||||||||
![]() |
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
![]() |
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
![]() |
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
![]() |
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
![]() |
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Extract RGB32x1 Details
![]() |
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 635
- Slice LUTs: 708
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 2
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 605
- Slice LUTs: 649
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 2
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 161
- Slice LUTs: 126
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 3
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 684
- Slice LUTs: 520
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Extract RGB32x8
Extracts (reduces) an image or part of an image with adjustment of the horizontal and vertical resolution.
Supported Image Types

![]() |
Optional Rectangle defines a four-element array that contains the left, top, right, and bottom coordinates of the region to process. The right and bottom values are exclusive and lie outside the region. The VI applies the operation to the entire image if Optional Rectangle is empty or not connected. |
||||||||||||||||||
![]() |
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
![]() |
Xstep is the vertical sampling step, which defines the columns to be extracted (the horizontal reduction ratio). For example, with an Xstep equal to 3, one out of every three columns is extracted from the Pixel Bus In into the Pixel Bus Out. Each column is extracted if the default value (1) is used. |
||||||||||||||||||
![]() |
Y Step Size is the horizontal sampling step, which defines the lines to be extracted (the vertical reduction ratio). Each row is extracted if the default value (1) is used. |
||||||||||||||||||
![]() |
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
![]() |
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
![]() |
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
![]() |
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
![]() |
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Extract RGB32x8 Details
![]() |
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 6021
- Slice LUTs: 11431
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 10
- Initiation Interval: 1
IMAQ FPGA Extract HSL32x1
Extracts (reduces) an image or part of an image with adjustment of the horizontal and vertical resolution.
Supported Image Types

![]() |
Optional Rectangle defines a four-element array that contains the left, top, right, and bottom coordinates of the region to process. The right and bottom values are exclusive and lie outside the region. The VI applies the operation to the entire image if Optional Rectangle is empty or not connected. |
||||||||||||||||||
![]() |
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
![]() |
Xstep is the vertical sampling step, which defines the columns to be extracted (the horizontal reduction ratio). For example, with an Xstep equal to 3, one out of every three columns is extracted from the Pixel Bus In into the Pixel Bus Out. Each column is extracted if the default value (1) is used. |
||||||||||||||||||
![]() |
Y Step Size is the horizontal sampling step, which defines the lines to be extracted (the vertical reduction ratio). Each row is extracted if the default value (1) is used. |
||||||||||||||||||
![]() |
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
![]() |
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
![]() |
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
![]() |
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
![]() |
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Extract HSL32x1 Details
![]() |
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 635
- Slice LUTs: 708
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 2
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 605
- Slice LUTs: 647
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 2
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 161
- Slice LUTs: 126
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 3
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 684
- Slice LUTs: 522
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Extract HSL32x8
Extracts (reduces) an image or part of an image with adjustment of the horizontal and vertical resolution.
Supported Image Types

![]() |
Optional Rectangle defines a four-element array that contains the left, top, right, and bottom coordinates of the region to process. The right and bottom values are exclusive and lie outside the region. The VI applies the operation to the entire image if Optional Rectangle is empty or not connected. |
||||||||||||||||||
![]() |
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
![]() |
Xstep is the vertical sampling step, which defines the columns to be extracted (the horizontal reduction ratio). For example, with an Xstep equal to 3, one out of every three columns is extracted from the Pixel Bus In into the Pixel Bus Out. Each column is extracted if the default value (1) is used. |
||||||||||||||||||
![]() |
Y Step Size is the horizontal sampling step, which defines the lines to be extracted (the vertical reduction ratio). Each row is extracted if the default value (1) is used. |
||||||||||||||||||
![]() |
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
![]() |
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
![]() |
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
![]() |
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
![]() |
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Extract HSL32x8 Details
![]() |
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 6021
- Slice LUTs: 11429
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 10
- Initiation Interval: 1













