IMAQ FPGA Equalize VI
- Updated2023-02-21
- 10 minute(s) read
Requires: NI Vision Development Module FPGA
Produces a histogram equalization of an image. This VI redistributes the pixel values of an image to linearize the accumulated histogram. The precision of the VI is dependent on the histogram precision, which in turn is dependent on the number of classes used in the histogram.
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Note This VI requires an FPGA target with DRAM. Currently, the only NI Vision hardware products that support DRAM are the NI PCIe-1473R and the NI PCIe-1473R-LX110. |
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Note This VI has variable latency, which is dependent on the image size. Plug the Minimum Latency value from the Estimated Performance section into the following formula to determine the total latency.
Total Latency = [Image Height * (Image Width + 1)] + Internal Latency Internal Latency:
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IMAQ FPGA Equalize NoMask U8x1
Produces a histogram equalization of an image. This VI redistributes the pixel values of an image to linearize the accumulated histogram. The minimum image size for the U8x1 instance of this VI should be more than 400 pixels. For instance, 20 x 20 or 10 x 40.
Supported Image Types
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Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
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Memory In is a reference to the external memory from which to transfer images. |
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Range is a cluster containing the minimum and maximum pixel values you want the resulting equalized image expanded to.
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Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
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Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
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Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
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Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
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IMAQ FPGA Equalize NoMask U8x1 Details
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Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 9711
- Slice LUTs: 11002
- DSP48s: 24
- Block RAMs: 16
Estimated Performance
- Minimum Latency: 639
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 10230
- Slice LUTs: 8444
- DSP48s: 18
- Block RAMs: 34
Estimated Performance
- Minimum Latency: 0
- Initiation Interval: 1
IMAQ FPGA Equalize NoMask U16x1
Produces a histogram equalization of an image. This VI redistributes the pixel values of an image to linearize the accumulated histogram. This instance only supports 12-bit images. The pixel value should be in the range of 0 to 4095. The minimum image size for this instance is 4900 pixels. For instance, 70 x 70 or 100 x 49.
Supported Image Types
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Dynamic Range is a cluster specifying the minimum and maximum pixel values in the image. Only those pixels having a value that falls in this range are taken into account by the histogram calculation. The range supported is 0 to 4096.
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Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
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Memory In is a reference to the external memory from which to transfer images. |
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Range is a cluster containing the minimum and maximum pixel values you want the resulting equalized image expanded to. Range should be a subset of Dynamic Range. For example, if the Dynamic Range is (10, 3020), the Minimum value for Range should be greater than 10 and the Maximum value should be less than 3020. The range supported is 0 to 4096.
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Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
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Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
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Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
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Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
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IMAQ FPGA Equalize NoMask U16x1 Details
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Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 3683
- Slice LUTs: 4026
- DSP48s: 7
- Block RAMs: 14
Estimated Performance
- Minimum Latency: 8316
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 7254
- Slice LUTs: 6278
- DSP48s: 7
- Block RAMs: 16
Estimated Performance
- Minimum Latency: 0
- Initiation Interval: 1