NI Vision for LabVIEW

IMAQ FPGA Edge Detection VI

  • Updated2023-02-21
  • 130 minute(s) read
Owning Palette: Filters
Requires: NI Vision Development Module FPGA

Extracts the contours (detects edges) in gray-level values. Refer to the NI Vision Concepts Help for more information about edge-detection filters.

Note  

This VI has variable latency, which is dependent on the image size. Plug the Minimum Latency value from the Estimated Performance section into the following formula to determine the total latency. All instances of this VI use a 3 x 3 kernel size. For the x1 VI instances, use this forumla to calculate the total latency:

  • Total Latency = Minimum Latency + (Image Width+2)((Kernel Size/2) - 0.5) + 3

For the x8 VI instances, use this forumla to calculate the total latency:

  • Total Latency = Minimum Latency + (Floor(Image Width/8)((Kernel Size/2) - 0.5) + 2)

IMAQ FPGA Differentiation U8 x1

Extracts the contours (detects edges) in gray-level values using a Differentiation filter.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA Differentiation U8 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu8.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ccclst.gif

Mask Pixel Bus In is an image that specifies the region of the image that will be copied. Only pixels in Pixel Bus In that correspond to a non-zero pixel in the mask image are copied. All other pixels are set to 0.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu8.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Differentiation U8 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 1266
  • Slice LUTs: 1515
  • DSP48s: 0
  • Block RAMs: 4

Estimated Performance

  • Minimum Latency: 19
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 1265
  • Slice LUTs: 1393
  • DSP48s: 0
  • Block RAMs: 8

Estimated Performance

  • Minimum Latency: 19
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 1478
  • Slice LUTs: 1239
  • DSP48s: 0
  • Block RAMs: 5

Estimated Performance

  • Minimum Latency: 17
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 1456
  • Slice LUTs: 1168
  • DSP48s: 0
  • Block RAMs: 5

Estimated Performance

  • Minimum Latency: 17
  • Initiation Interval: 1

IMAQ FPGA Differentiation U16 x1

Extracts the contours (detects edges) in gray-level values using a Differentiation filter.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA Differentiation U16 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu16.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ccclst.gif

Mask Pixel Bus In is an image that specifies the region of the image that will be copied. Only pixels in Pixel Bus In that correspond to a non-zero pixel in the mask image are copied. All other pixels are set to 0.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu16.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Differentiation U16 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 1760
  • Slice LUTs: 2093
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 19
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 1760
  • Slice LUTs: 1951
  • DSP48s: 0
  • Block RAMs: 14

Estimated Performance

  • Minimum Latency: 19
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 2068
  • Slice LUTs: 1570
  • DSP48s: 0
  • Block RAMs: 8

Estimated Performance

  • Minimum Latency: 17
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 2046
  • Slice LUTs: 1545
  • DSP48s: 0
  • Block RAMs: 8

Estimated Performance

  • Minimum Latency: 17
  • Initiation Interval: 1

IMAQ FPGA Gradient U8 x1

Extracts the contours (detects edges) in gray-level values using a Gradient filter.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA Gradient U8 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu8.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ccclst.gif

Mask Pixel Bus In is an image that specifies the region of the image that will be copied. Only pixels in Pixel Bus In that correspond to a non-zero pixel in the mask image are copied. All other pixels are set to 0.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu8.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Gradient U8 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 1257
  • Slice LUTs: 1482
  • DSP48s: 0
  • Block RAMs: 4

Estimated Performance

  • Minimum Latency: 18
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 1256
  • Slice LUTs: 1368
  • DSP48s: 0
  • Block RAMs: 8

Estimated Performance

  • Minimum Latency: 18
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 1468
  • Slice LUTs: 1210
  • DSP48s: 0
  • Block RAMs: 5

Estimated Performance

  • Minimum Latency: 17
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 1446
  • Slice LUTs: 1144
  • DSP48s: 0
  • Block RAMs: 5

Estimated Performance

  • Minimum Latency: 17
  • Initiation Interval: 1

IMAQ FPGA Gradient U16 x1

Extracts the contours (detects edges) in gray-level values using a Gradient filter.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA Gradient U16 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu16.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ccclst.gif

Mask Pixel Bus In is an image that specifies the region of the image that will be copied. Only pixels in Pixel Bus In that correspond to a non-zero pixel in the mask image are copied. All other pixels are set to 0.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu16.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Gradient U16 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 1743
  • Slice LUTs: 2011
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 19
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 1743
  • Slice LUTs: 1869
  • DSP48s: 0
  • Block RAMs: 14

Estimated Performance

  • Minimum Latency: 19
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 2051
  • Slice LUTs: 1506
  • DSP48s: 0
  • Block RAMs: 8

Estimated Performance

  • Minimum Latency: 17
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 2029
  • Slice LUTs: 1478
  • DSP48s: 0
  • Block RAMs: 8

Estimated Performance

  • Minimum Latency: 17
  • Initiation Interval: 1

IMAQ FPGA Prewitt U8 x1

Extracts the contours (detects edges) in gray-level values using a Prewitt filter.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA Prewitt U8 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu8.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ccclst.gif

Mask Pixel Bus In is an image that specifies the region of the image that will be copied. Only pixels in Pixel Bus In that correspond to a non-zero pixel in the mask image are copied. All other pixels are set to 0.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu8.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Prewitt U8 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 1562
  • Slice LUTs: 1783
  • DSP48s: 1
  • Block RAMs: 4

Estimated Performance

  • Minimum Latency: 21
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 1558
  • Slice LUTs: 1624
  • DSP48s: 1
  • Block RAMs: 8

Estimated Performance

  • Minimum Latency: 21
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 1772
  • Slice LUTs: 1355
  • DSP48s: 1
  • Block RAMs: 5

Estimated Performance

  • Minimum Latency: 19
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 1750
  • Slice LUTs: 1333
  • DSP48s: 1
  • Block RAMs: 5

Estimated Performance

  • Minimum Latency: 19
  • Initiation Interval: 1

IMAQ FPGA Prewitt U16 x1

Extracts the contours (detects edges) in gray-level values using a Prewitt filter.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA Prewitt U16 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu16.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ccclst.gif

Mask Pixel Bus In is an image that specifies the region of the image that will be copied. Only pixels in Pixel Bus In that correspond to a non-zero pixel in the mask image are copied. All other pixels are set to 0.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu16.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Prewitt U16 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 2367
  • Slice LUTs: 2709
  • DSP48s: 2
  • Block RAMs: 7

Estimated Performance

  • Minimum Latency: 22
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 2499
  • Slice LUTs: 2474
  • DSP48s: 2
  • Block RAMs: 14

Estimated Performance

  • Minimum Latency: 22
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 4522
  • Slice LUTs: 4095
  • DSP48s: 2
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 19
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 2694
  • Slice LUTs: 2105
  • DSP48s: 2
  • Block RAMs: 8

Estimated Performance

  • Minimum Latency: 19
  • Initiation Interval: 1

IMAQ FPGA Roberts U8 x1

Extracts the contours (detects edges) in gray-level values using a Roberts filter.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA Roberts U8 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu8.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ccclst.gif

Mask Pixel Bus In is an image that specifies the region of the image that will be copied. Only pixels in Pixel Bus In that correspond to a non-zero pixel in the mask image are copied. All other pixels are set to 0.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu8.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Roberts U8 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 1258
  • Slice LUTs: 1423
  • DSP48s: 0
  • Block RAMs: 4

Estimated Performance

  • Minimum Latency: 18
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 1257
  • Slice LUTs: 1316
  • DSP48s: 0
  • Block RAMs: 8

Estimated Performance

  • Minimum Latency: 18
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 1469
  • Slice LUTs: 1180
  • DSP48s: 0
  • Block RAMs: 5

Estimated Performance

  • Minimum Latency: 17
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 1447
  • Slice LUTs: 1160
  • DSP48s: 0
  • Block RAMs: 5

Estimated Performance

  • Minimum Latency: 17
  • Initiation Interval: 1

IMAQ FPGA Roberts U16 x1

Extracts the contours (detects edges) in gray-level values using a Roberts filter.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA Roberts U16 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu16.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ccclst.gif

Mask Pixel Bus In is an image that specifies the region of the image that will be copied. Only pixels in Pixel Bus In that correspond to a non-zero pixel in the mask image are copied. All other pixels are set to 0.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu16.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Roberts U16 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 1744
  • Slice LUTs: 1892
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 19
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 1744
  • Slice LUTs: 1735
  • DSP48s: 0
  • Block RAMs: 14

Estimated Performance

  • Minimum Latency: 19
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 2052
  • Slice LUTs: 1507
  • DSP48s: 0
  • Block RAMs: 8

Estimated Performance

  • Minimum Latency: 17
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 2030
  • Slice LUTs: 1473
  • DSP48s: 0
  • Block RAMs: 8

Estimated Performance

  • Minimum Latency: 17
  • Initiation Interval: 1

IMAQ FPGA Sigma U8 x1

Extracts the contours (detects edges) in gray-level values using a Sigma filter.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA Sigma U8 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu8.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ccclst.gif

Mask Pixel Bus In is an image that specifies the region of the image that will be copied. Only pixels in Pixel Bus In that correspond to a non-zero pixel in the mask image are copied. All other pixels are set to 0.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu8.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Sigma U8 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 1503
  • Slice LUTs: 1749
  • DSP48s: 0
  • Block RAMs: 4

Estimated Performance

  • Minimum Latency: 18
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 1507
  • Slice LUTs: 1659
  • DSP48s: 0
  • Block RAMs: 8

Estimated Performance

  • Minimum Latency: 18
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 1737
  • Slice LUTs: 1356
  • DSP48s: 0
  • Block RAMs: 5

Estimated Performance

  • Minimum Latency: 16
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 1715
  • Slice LUTs: 1337
  • DSP48s: 0
  • Block RAMs: 5

Estimated Performance

  • Minimum Latency: 16
  • Initiation Interval: 1

IMAQ FPGA Sigma U16 x1

Extracts the contours (detects edges) in gray-level values using a Sigma filter.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA Sigma U16 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu16.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ccclst.gif

Mask Pixel Bus In is an image that specifies the region of the image that will be copied. Only pixels in Pixel Bus In that correspond to a non-zero pixel in the mask image are copied. All other pixels are set to 0.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu16.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Sigma U16 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 2213
  • Slice LUTs: 2704
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 18
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 2229
  • Slice LUTs: 2567
  • DSP48s: 0
  • Block RAMs: 14

Estimated Performance

  • Minimum Latency: 18
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 2644
  • Slice LUTs: 2048
  • DSP48s: 0
  • Block RAMs: 8

Estimated Performance

  • Minimum Latency: 16
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 2622
  • Slice LUTs: 2024
  • DSP48s: 0
  • Block RAMs: 8

Estimated Performance

  • Minimum Latency: 16
  • Initiation Interval: 1

IMAQ FPGA Sobel U8 x1

Extracts the contours (detects edges) in gray-level values using a Sobel filter.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA Sobel U8 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu8.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ccclst.gif

Mask Pixel Bus In is an image that specifies the region of the image that will be copied. Only pixels in Pixel Bus In that correspond to a non-zero pixel in the mask image are copied. All other pixels are set to 0.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu8.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Sobel U8 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 1522
  • Slice LUTs: 1713
  • DSP48s: 0
  • Block RAMs: 4

Estimated Performance

  • Minimum Latency: 19
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 1533
  • Slice LUTs: 1591
  • DSP48s: 0
  • Block RAMs: 8

Estimated Performance

  • Minimum Latency: 19
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 1745
  • Slice LUTs: 1325
  • DSP48s: 0
  • Block RAMs: 5

Estimated Performance

  • Minimum Latency: 17
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 8612
  • Slice LUTs: 6507
  • DSP48s: 0
  • Block RAMs: 23

Estimated Performance

  • Minimum Latency: 17
  • Initiation Interval: 1

IMAQ FPGA Sobel U16 x1

Extracts the contours (detects edges) in gray-level values using a Sobel filter.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA Sobel U16 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu16.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ccclst.gif

Mask Pixel Bus In is an image that specifies the region of the image that will be copied. Only pixels in Pixel Bus In that correspond to a non-zero pixel in the mask image are copied. All other pixels are set to 0.

cbool.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu16.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Sobel U16 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 2370
  • Slice LUTs: 2593
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 20
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 2400
  • Slice LUTs: 2423
  • DSP48s: 0
  • Block RAMs: 14

Estimated Performance

  • Minimum Latency: 20
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 2625
  • Slice LUTs: 2104
  • DSP48s: 0
  • Block RAMs: 8

Estimated Performance

  • Minimum Latency: 18
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 2603
  • Slice LUTs: 2171
  • DSP48s: 0
  • Block RAMs: 8

Estimated Performance

  • Minimum Latency: 18
  • Initiation Interval: 1

IMAQ FPGA Differentiation NoMask U8 x1

Extracts the contours (detects edges) in gray-level values using a Differentiation filter.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA Differentiation NoMask U8 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu8.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu8.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Differentiation NoMask U8 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 1053
  • Slice LUTs: 1230
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 11
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 1053
  • Slice LUTs: 1123
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 11
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 1228
  • Slice LUTs: 1075
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 9
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 1206
  • Slice LUTs: 1036
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 9
  • Initiation Interval: 1

IMAQ FPGA Differentiation NoMask U8 x8

Extracts the contours (detects edges) in gray-level values using a Differentiation filter.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA Differentiation NoMask U8 x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu8.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu8.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Differentiation NoMask U8 x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 2913
  • Slice LUTs: 2685
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 12
  • Initiation Interval: 1

IMAQ FPGA Differentiation NoMask U16 x1

Extracts the contours (detects edges) in gray-level values using a Differentiation filter.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA Differentiation NoMask U16 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu16.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu16.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Differentiation NoMask U16 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 1116
  • Slice LUTs: 1398
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 11
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 1108
  • Slice LUTs: 1308
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 11
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 1364
  • Slice LUTs: 1253
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 9
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 1789
  • Slice LUTs: 1413
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 9
  • Initiation Interval: 1

IMAQ FPGA Differentiation NoMask U16 x8

Extracts the contours (detects edges) in gray-level values using a Differentiation filter.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA Differentiation NoMask U16 x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu16.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu16.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Differentiation NoMask U16 x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 4820
  • Slice LUTs: 4887
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 12
  • Initiation Interval: 1

IMAQ FPGA Gradient NoMask U8 x1

Extracts the contours (detects edges) in gray-level values using a Gradient filter.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA Gradient NoMask U8 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu8.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu8.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Gradient NoMask U8 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 1018
  • Slice LUTs: 1213
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 10
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 1018
  • Slice LUTs: 1085
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 10
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 1228
  • Slice LUTs: 996
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 9
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 1206
  • Slice LUTs: 969
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 9
  • Initiation Interval: 1

IMAQ FPGA Gradient NoMask U8 x8

Extracts the contours (detects edges) in gray-level values using a Gradient filter.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA Gradient NoMask U8 x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu8.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu8.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Gradient NoMask U8 x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 2474
  • Slice LUTs: 2137
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 11
  • Initiation Interval: 1

IMAQ FPGA Gradient NoMask U16 x1

Extracts the contours (detects edges) in gray-level values using a Gradient filter.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA Gradient NoMask U16 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu16.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu16.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Gradient NoMask U16 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 1107
  • Slice LUTs: 1311
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 11
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 1099
  • Slice LUTs: 1174
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 11
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 1330
  • Slice LUTs: 1221
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 9
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 1756
  • Slice LUTs: 1485
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 9
  • Initiation Interval: 1

IMAQ FPGA Gradient NoMask U16 x8

Extracts the contours (detects edges) in gray-level values using a Gradient filter.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA Gradient NoMask U16 x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu16.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu16.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Gradient NoMask U16 x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 4557
  • Slice LUTs: 3973
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 12
  • Initiation Interval: 1

IMAQ FPGA Prewitt NoMask U8 x1

Extracts the contours (detects edges) in gray-level values using a Prewitt filter.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA Prewitt NoMask U8 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu8.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu8.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Prewitt NoMask U8 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 1312
  • Slice LUTs: 1503
  • DSP48s: 1
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 13
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 1306
  • Slice LUTs: 1447
  • DSP48s: 1
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 13
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 1554
  • Slice LUTs: 1357
  • DSP48s: 1
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 11
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 1532
  • Slice LUTs: 1334
  • DSP48s: 1
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 11
  • Initiation Interval: 1

IMAQ FPGA Prewitt NoMask U8 x8

Extracts the contours (detects edges) in gray-level values using a Prewitt filter.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA Prewitt NoMask U8 x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu8.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu8.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Prewitt NoMask U8 x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 3307
  • Slice LUTs: 3131
  • DSP48s: 8
  • Block RAMs: 5

Estimated Performance

  • Minimum Latency: 13
  • Initiation Interval: 1

IMAQ FPGA Prewitt NoMask U16 x1

Extracts the contours (detects edges) in gray-level values using a Prewitt filter.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA Prewitt NoMask U16 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu16.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu16.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Prewitt NoMask U16 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 2078
  • Slice LUTs: 2276
  • DSP48s: 2
  • Block RAMs: 5

Estimated Performance

  • Minimum Latency: 14
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 2208
  • Slice LUTs: 2068
  • DSP48s: 2
  • Block RAMs: 12

Estimated Performance

  • Minimum Latency: 14
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 4230
  • Slice LUTs: 3996
  • DSP48s: 2
  • Block RAMs: 10

Estimated Performance

  • Minimum Latency: 11
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 2403
  • Slice LUTs: 2004
  • DSP48s: 2
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 11
  • Initiation Interval: 1

IMAQ FPGA Prewitt NoMask U16 x8

Extracts the contours (detects edges) in gray-level values using a Prewitt filter.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA Prewitt NoMask U16 x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu16.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu16.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Prewitt NoMask U16 x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 6200
  • Slice LUTs: 5407
  • DSP48s: 16
  • Block RAMs: 8

Estimated Performance

  • Minimum Latency: 15
  • Initiation Interval: 1

IMAQ FPGA Roberts NoMask U8 x1

Extracts the contours (detects edges) in gray-level values using a Roberts filter.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA Roberts NoMask U8 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu8.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu8.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Roberts NoMask U8 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 1018
  • Slice LUTs: 1213
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 10
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 1018
  • Slice LUTs: 1088
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 10
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 1228
  • Slice LUTs: 996
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 9
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 1206
  • Slice LUTs: 970
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 9
  • Initiation Interval: 1

IMAQ FPGA Roberts NoMask U8 x8

Extracts the contours (detects edges) in gray-level values using a Roberts filter.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA Roberts NoMask U8 x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu8.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu8.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Roberts NoMask U8 x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 2537
  • Slice LUTs: 2339
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 11
  • Initiation Interval: 1

IMAQ FPGA Roberts NoMask U16 x1

Extracts the contours (detects edges) in gray-level values using a Roberts filter.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA Roberts NoMask U16 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu16.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu16.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Roberts NoMask U16 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 1107
  • Slice LUTs: 1311
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 11
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 1099
  • Slice LUTs: 1180
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 11
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 1330
  • Slice LUTs: 1224
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 9
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 1756
  • Slice LUTs: 1483
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 9
  • Initiation Interval: 1

IMAQ FPGA Roberts NoMask U16 x8

Extracts the contours (detects edges) in gray-level values using a Roberts filter.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA Roberts NoMask U16 x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu16.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu16.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Roberts NoMask U16 x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 4676
  • Slice LUTs: 4301
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 12
  • Initiation Interval: 1

IMAQ FPGA Sigma NoMask U8 x1

Extracts the contours (detects edges) in gray-level values using a Sigma filter.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA Sigma NoMask U8 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu8.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu8.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Sigma NoMask U8 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 1273
  • Slice LUTs: 1489
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 10
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 1278
  • Slice LUTs: 1398
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 10
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 1483
  • Slice LUTs: 1283
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 8
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 1461
  • Slice LUTs: 1252
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 8
  • Initiation Interval: 1

IMAQ FPGA Sigma NoMask U8 x8

Extracts the contours (detects edges) in gray-level values using a Sigma filter.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA Sigma NoMask U8 x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu8.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu8.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Sigma NoMask U8 x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 3148
  • Slice LUTs: 3656
  • DSP48s: 0
  • Block RAMs: 5

Estimated Performance

  • Minimum Latency: 11
  • Initiation Interval: 1

IMAQ FPGA Sigma NoMask U16 x1

Extracts the contours (detects edges) in gray-level values using a Sigma filter.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA Sigma NoMask U16 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu16.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu16.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Sigma NoMask U16 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 1335
  • Slice LUTs: 1685
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 10
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 1349
  • Slice LUTs: 1597
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 10
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 1592
  • Slice LUTs: 1673
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 8
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 2266
  • Slice LUTs: 2241
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 8
  • Initiation Interval: 1

IMAQ FPGA Sigma NoMask U16 x8

Extracts the contours (detects edges) in gray-level values using a Sigma filter.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA Sigma NoMask U16 x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu16.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu16.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Sigma NoMask U16 x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 5571
  • Slice LUTs: 7345
  • DSP48s: 0
  • Block RAMs: 8

Estimated Performance

  • Minimum Latency: 11
  • Initiation Interval: 1

IMAQ FPGA Sobel NoMask U8 x1

Extracts the contours (detects edges) in gray-level values using a Sobel filter.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA Sobel NoMask U8 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu8.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu8.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Sobel NoMask U8 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 1284
  • Slice LUTs: 1451
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 11
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 1296
  • Slice LUTs: 1423
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 11
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 1480
  • Slice LUTs: 1301
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 9
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 1458
  • Slice LUTs: 1399
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 9
  • Initiation Interval: 1

IMAQ FPGA Sobel NoMask U8 x8

Extracts the contours (detects edges) in gray-level values using a Sobel filter.

Instance Details

Supported Image Types

8-bit unsigned grayscale

IMAQ FPGA Sobel NoMask U8 x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu8.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu8.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Sobel NoMask U8 x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 3197
  • Slice LUTs: 3106
  • DSP48s: 0
  • Block RAMs: 5

Estimated Performance

  • Minimum Latency: 12
  • Initiation Interval: 1

IMAQ FPGA Sobel NoMask U16 x1

Extracts the contours (detects edges) in gray-level values using a Sobel filter.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA Sobel NoMask U16 x1

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu16.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu16.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Sobel NoMask U16 x1 Details

Note  Resource estimates are based on a 40 MHz clock.

Virtex-5

Estimated Device Utilization

  • Slice Registers: 1375
  • Slice LUTs: 1597
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 12
  • Initiation Interval: 1

Spartan-6

Estimated Device Utilization

  • Slice Registers: 1381
  • Slice LUTs: 1454
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 12
  • Initiation Interval: 1

Zynq

Estimated Device Utilization

  • Slice Registers: 1624
  • Slice LUTs: 1513
  • DSP48s: 0
  • Block RAMs: 3

Estimated Performance

  • Minimum Latency: 10
  • Initiation Interval: 1

Kintex-7

Estimated Device Utilization

  • Slice Registers: 2297
  • Slice LUTs: 1951
  • DSP48s: 0
  • Block RAMs: 6

Estimated Performance

  • Minimum Latency: 10
  • Initiation Interval: 1

IMAQ FPGA Sobel NoMask U16 x8

Extracts the contours (detects edges) in gray-level values using a Sobel filter.

Instance Details

Supported Image Types

16-bit unsigned grayscale

IMAQ FPGA Sobel NoMask U16 x8

ccclst.gif

Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

cu16.gif

Pixel Data is the value of the pixel.

cbool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

cbool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

cbool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

cenum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

cfxp.gif

Threshold Value is the minimum pixel value to appear in the resulting image. It is rare to use a value greater than 0 for this type of processing because the results from this processing are usually very dark and are not very dynamic. The default is 0.

cbool.gif

Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node.

cbool.gif

Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.

Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle.
icclst.gif

Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.

iu16.gif

Pixel Data is the value of the pixel.

ibool.gif

DV Data valid. Determines whether the Pixel Data element should be use (TRUE) or ignored (FALSE).

ibool.gif

EOL End of line. When TRUE, indicates that the end of the line has been reached.

ibool.gif

EOI End of image. When TRUE, indicates that the end of the image has been reached.

ienum.gif

Data Type is used in the block diagram for determining the type of the Pixel Bus. Unused during processing and gets optimized out of the compiled bit stream.

ibool.gif

Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node.

ibool.gif

Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.

Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the Input Valid terminal is TRUE during the following cycle.

IMAQ FPGA Sobel NoMask U16 x8 Details

Note  Resource estimates are based on a 40 MHz clock.

Kintex-7

Estimated Device Utilization

  • Slice Registers: 5804
  • Slice LUTs: 5240
  • DSP48s: 0
  • Block RAMs: 8

Estimated Performance

  • Minimum Latency: 12
  • Initiation Interval: 1