IMAQ FPGA ColorThreshold VI
- Updated2023-02-21
- 29 minute(s) read
Requires: NI Vision Development Module FPGA
Applies a threshold to the three planes of an RGB or HSL image and places the result into an image.
IMAQ FPGA ColorThreshold RGB32 x1
Applies a threshold to the three planes of an RGB image and places the result into an image.
Supported Image Types
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Blue Range determines the thresholding range for the blue plane. Any pixels not included in this range are reset to 0 in the Pixel Bus Out.
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Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
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Red Range determines the thresholding range for the green plane. Any pixels not included in this range are reset to 0 in the Pixel Bus Out.
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Green Range determines the thresholding range for the green plane. Any pixels not included in this range are reset to 0 in the Pixel Bus Out.
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Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
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Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
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Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
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Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
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IMAQ FPGA ColorThreshold RGB32 x1 Details
 |
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 158
- Slice LUTs: 174
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 157
- Slice LUTs: 171
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 158
- Slice LUTs: 172
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 407
- Slice LUTs: 455
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA ColorThreshold RGB32 x8
Applies a threshold to the three planes of an RGB image and places the result into an image.
Supported Image Types
|
Blue Range determines the thresholding range for the blue plane. Any pixels not included in this range are reset to 0 in the Pixel Bus Out.
|
||||||||||||||||||
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Red Range determines the thresholding range for the green plane. Any pixels not included in this range are reset to 0 in the Pixel Bus Out.
|
||||||||||||||||||
|
Green Range determines the thresholding range for the green plane. Any pixels not included in this range are reset to 0 in the Pixel Bus Out.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA ColorThreshold RGB32 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 518
- Slice LUTs: 720
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA ColorThreshold HSL32 x1
Applies a threshold to the three planes of an HSL image and places the result into an image.
Supported Image Types
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Lum Range determines the thresholding range for the luminance plane. Any pixels not included in this range are reset to 0 in the Pixel Bus Out.
|
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Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
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|
Hue Range determines the thresholding range for the hue plane. Any pixels not included in this range are reset to 0 in the Pixel Bus Out.
|
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Sat Range determines the thresholding range for the saturation plane. Any pixels not included in this range are reset to 0 in the Pixel Bus Out.
|
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Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA ColorThreshold HSL32 x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 158
- Slice LUTs: 174
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 157
- Slice LUTs: 171
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 158
- Slice LUTs: 172
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 163
- Slice LUTs: 182
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA ColorThreshold HSL32 x8
Applies a threshold to the three planes of an HSL image and places the result into an image.
Supported Image Types
|
Lum Range determines the thresholding range for the luminance plane. Any pixels not included in this range are reset to 0 in the Pixel Bus Out.
|
||||||||||||||||||
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Hue Range determines the thresholding range for the hue plane. Any pixels not included in this range are reset to 0 in the Pixel Bus Out.
|
||||||||||||||||||
|
Sat Range determines the thresholding range for the saturation plane. Any pixels not included in this range are reset to 0 in the Pixel Bus Out.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA ColorThreshold HSL32 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 518
- Slice LUTs: 720
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA ColorThreshold RGBTOHSL32 x1
Applies a threshold to the three planes of an RGB image and places the result into an image.
Supported Image Types
|
Lum Range determines the thresholding range for the luminance plane. Any pixels not included in this range are reset to 0 in the Pixel Bus Out.
|
||||||||||||||||||
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Hue Range determines the thresholding range for the hue plane. Any pixels not included in this range are reset to 0 in the Pixel Bus Out.
|
||||||||||||||||||
|
Sat Range determines the thresholding range for the saturation plane. Any pixels not included in this range are reset to 0 in the Pixel Bus Out.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA ColorThreshold RGBTOHSL32 x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 3222
- Slice LUTs: 4191
- DSP48s: 15
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 37
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 3104
- Slice LUTs: 3654
- DSP48s: 27
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 37
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 3490
- Slice LUTs: 4623
- DSP48s: 20
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 30
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 6774
- Slice LUTs: 9122
- DSP48s: 40
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 30
- Initiation Interval: 1
IMAQ FPGA ColorThreshold RGBTOHSL32 x8
Applies a threshold to the three planes of an RGB image and places the result into an image.
Supported Image Types
|
Lum Range determines the thresholding range for the luminance plane. Any pixels not included in this range are reset to 0 in the Pixel Bus Out.
|
||||||||||||||||||
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Hue Range determines the thresholding range for the hue plane. Any pixels not included in this range are reset to 0 in the Pixel Bus Out.
|
||||||||||||||||||
|
Sat Range determines the thresholding range for the saturation plane. Any pixels not included in this range are reset to 0 in the Pixel Bus Out.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA ColorThreshold RGBTOHSL32 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 16430
- Slice LUTs: 29107
- DSP48s: 96
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 32
- Initiation Interval: 1