IMAQ FPGA Cast VI
- Updated2023-02-21
- 140 minute(s) read
Converts the current image type to another image type. Refer to the NI Vision Concepts Help for more information about converting image types.
IMAQ FPGA Cast U1x1 to U8x1
Converts a U1 image to a U8 image.
Supported Image Types
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Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
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Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
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 |
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
 |
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
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|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
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IMAQ FPGA Cast U1x1 to U8x1 Details
 |
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 79
- Slice LUTs: 80
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 80
- Slice LUTs: 76
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 79
- Slice LUTs: 60
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 85
- Slice LUTs: 72
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast U1x8 to U8x8
Converts a U1 image to a U8 image.
Supported Image Types
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Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast U1x8 to U8x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 203
- Slice LUTs: 156
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast U1x1 to U16x1
Converts a U1 image to a U16 image.
Supported Image Types
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Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast U1x1 to U16x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 94
- Slice LUTs: 100
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 93
- Slice LUTs: 95
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 94
- Slice LUTs: 75
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 99
- Slice LUTs: 89
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast U1x8 to U16x8
Converts a U1 image to a U16 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast U1x8 to U16x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 274
- Slice LUTs: 196
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast U1x1 to RGB32x1
Converts a U1 image to an RGB32 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast U1x1 to RGB32x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 114
- Slice LUTs: 124
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 113
- Slice LUTs: 120
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 110
- Slice LUTs: 86
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 115
- Slice LUTs: 99
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast U1x8 to RGB32x8
Converts a U1 image to an RGB32 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast U1x8 to RGB32x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 470
- Slice LUTs: 310
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast U1x1 to HSL32x1
Converts a U1 image to an HSL32 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast U1x1 to HSL32x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 110
- Slice LUTs: 122
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 109
- Slice LUTs: 118
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 110
- Slice LUTs: 86
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 115
- Slice LUTs: 98
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast U1x8 to HSL32x8
Converts a U1 image to an HSL32 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast U1x8 to HSL32x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 470
- Slice LUTs: 311
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast U8x1 to U1x1
Converts a U8 image to a U1 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast U8x1 to U1x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 79
- Slice LUTs: 76
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 80
- Slice LUTs: 72
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 79
- Slice LUTs: 62
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 211
- Slice LUTs: 183
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast U8x8 to U1x8
Converts a U8 image to a U1 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast U8x8 to U1x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 203
- Slice LUTs: 177
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast U8x1 to U16x1
Converts a U8 image to a U16 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast U8x1 to U16x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 115
- Slice LUTs: 110
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 114
- Slice LUTs: 105
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 115
- Slice LUTs: 90
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 120
- Slice LUTs: 103
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast U8x8 to U16x8
Converts a U8 image to a U16 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast U8x8 to U16x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 442
- Slice LUTs: 305
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast U8x1 to RGB32x1
Converts a U8 image to an RGB32 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast U8x1 to RGB32x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 163
- Slice LUTs: 148
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 162
- Slice LUTs: 142
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 131
- Slice LUTs: 106
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 136
- Slice LUTs: 120
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast U8x8 to RGB32x8
Converts a U8 image to an RGB32 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast U8x8 to RGB32x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 638
- Slice LUTs: 485
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast U8x1 to HSL32x1
Converts a U8 image to an HSL32 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast U8x1 to HSL32x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 131
- Slice LUTs: 132
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 130
- Slice LUTs: 128
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 131
- Slice LUTs: 99
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 136
- Slice LUTs: 112
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast U8x8 to HSL32x8
Converts a U8 image to an HSL32 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast U8x8 to HSL32x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 638
- Slice LUTs: 485
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast U16x1 to U1x1
Converts a U16 image to a U1 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast U16x1 to U1x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 94
- Slice LUTs: 102
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 93
- Slice LUTs: 98
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 94
- Slice LUTs: 91
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 99
- Slice LUTs: 104
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast U16x8 to U1x8
Converts a U16 image to a U1 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast U16x8 to U1x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 274
- Slice LUTs: 311
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast U16x1 to U8x1
Converts a U16 image to a U8 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
 |
# Shifts specifies the number of right shifts by which each pixel value in the input image is shifted. This is valid only when converting from a 16-bit image to an 8-bit image. The VI executes this conversion by shifting the 16-bit pixel values to the right by the specified number of shift operations, up to a maximum of 8 shift operations, and then truncating to get an 8-bit value. Enter a value of –1 to ignore the bit depth and shift 0. Enter a value of 0 to use the bit depth to cast the image. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast U16x1 to U8x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 123
- Slice LUTs: 169
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 122
- Slice LUTs: 171
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 123
- Slice LUTs: 155
- DSP48s: 1
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 128
- Slice LUTs: 163
- DSP48s: 1
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast U16x8 to U8x8
Converts a U16 image to a U8 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
# Shifts specifies the number of right shifts by which each pixel value in the input image is shifted. This is valid only when converting from a 16-bit image to an 8-bit image. The VI executes this conversion by shifting the 16-bit pixel values to the right by the specified number of shift operations, up to a maximum of 8 shift operations, and then truncating to get an 8-bit value. Enter a value of –1 to ignore the bit depth and shift 0. Enter a value of 0 to use the bit depth to cast the image. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast U16x8 to U8x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 450
- Slice LUTs: 563
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast U16x1 to RGB32x1
Converts a U16 image to an RGB32 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
# Shifts specifies the number of right shifts by which each pixel value in the input image is shifted. This is valid only when converting from a 16-bit image to an 8-bit image. The VI executes this conversion by shifting the 16-bit pixel values to the right by the specified number of shift operations, up to a maximum of 8 shift operations, and then truncating to get an 8-bit value. Enter a value of –1 to ignore the bit depth and shift 0. Enter a value of 0 to use the bit depth to cast the image. |
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast U16x1 to RGB32x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 179
- Slice LUTs: 156
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 178
- Slice LUTs: 151
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 147
- Slice LUTs: 122
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 152
- Slice LUTs: 186
- DSP48s: 1
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast U16x8 to RGB32x8
Converts a U16 image to an RGB32 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
# Shifts specifies the number of right shifts by which each pixel value in the input image is shifted. This is valid only when converting from a 16-bit image to an 8-bit image. The VI executes this conversion by shifting the 16-bit pixel values to the right by the specified number of shift operations, up to a maximum of 8 shift operations, and then truncating to get an 8-bit value. Enter a value of –1 to ignore the bit depth and shift 0. Enter a value of 0 to use the bit depth to cast the image. |
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast U16x8 to RGB32x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 710
- Slice LUTs: 934
- DSP48s: 8
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast U16x1 to HSL32x1
Converts a U16 image to an HSL32 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
# Shifts specifies the number of right shifts by which each pixel value in the input image is shifted. This is valid only when converting from a 16-bit image to an 8-bit image. The VI executes this conversion by shifting the 16-bit pixel values to the right by the specified number of shift operations, up to a maximum of 8 shift operations, and then truncating to get an 8-bit value. Enter a value of –1 to ignore the bit depth and shift 0. Enter a value of 0 to use the bit depth to cast the image. |
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast U16x1 to HSL32x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 147
- Slice LUTs: 141
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 146
- Slice LUTs: 139
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 147
- Slice LUTs: 115
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 152
- Slice LUTs: 179
- DSP48s: 1
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast U16x8 to HSL32x8
Converts a U16 image to an HSL32 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
# Shifts specifies the number of right shifts by which each pixel value in the input image is shifted. This is valid only when converting from a 16-bit image to an 8-bit image. The VI executes this conversion by shifting the 16-bit pixel values to the right by the specified number of shift operations, up to a maximum of 8 shift operations, and then truncating to get an 8-bit value. Enter a value of –1 to ignore the bit depth and shift 0. Enter a value of 0 to use the bit depth to cast the image. |
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast U16x8 to HSL32x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 710
- Slice LUTs: 934
- DSP48s: 8
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast RGB32x1 to U1x1
Converts an RGB32 image to a U1 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast RGB32x1 to U1x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 110
- Slice LUTs: 96
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 109
- Slice LUTs: 93
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 110
- Slice LUTs: 93
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 115
- Slice LUTs: 106
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast RGB32x8 to U1x8
Converts an RGB32 image to a U1 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast RGB32x8 to U1x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 470
- Slice LUTs: 377
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast RGB32x1 to U8x1
Converts an RGB32 image to a U8 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast RGB32x1 to U8x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 132
- Slice LUTs: 142
- DSP48s: 1
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 131
- Slice LUTs: 135
- DSP48s: 1
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 131
- Slice LUTs: 130
- DSP48s: 1
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 136
- Slice LUTs: 142
- DSP48s: 1
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast RGB32x8 to U8x8
Converts an RGB32 image to a U8 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast RGB32x8 to U8x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 638
- Slice LUTs: 662
- DSP48s: 8
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast RGB32x1 to U16x1
Converts an RGB32 image to a U16 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast RGB32x1 to U16x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 146
- Slice LUTs: 158
- DSP48s: 1
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 145
- Slice LUTs: 138
- DSP48s: 1
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 145
- Slice LUTs: 140
- DSP48s: 1
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 150
- Slice LUTs: 152
- DSP48s: 1
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast RGB32x8 to U16x8
Converts an RGB32 image to a U16 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast RGB32x8 to U16x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 750
- Slice LUTs: 754
- DSP48s: 8
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast RGB32x1 to HSL32x1
Converts an RGB32 image to an HSL32 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
 |
Offset adds an offset to the calculated Hue value when Color Mode is set to HSL. The offset represents the angle by which the hue plane is rotated. Offset can range from 0 to 360. The default offset value of 0 results in a hue value of 0 for the color red (R=255, G=0, B=0). By changing the offset value, you can specify the RGB color that maps to a hue value of 0. When you want to analyze red or colors close to red in the HSL space, you can add an offset so that the hue values associated with these colors are not zero. |
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast RGB32x1 to HSL32x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 3313
- Slice LUTs: 4302
- DSP48s: 15
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 37
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 3196
- Slice LUTs: 3698
- DSP48s: 27
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 37
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 3566
- Slice LUTs: 4653
- DSP48s: 20
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 30
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 1386
- Slice LUTs: 1840
- DSP48s: 8
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 30
- Initiation Interval: 1
IMAQ FPGA Cast RGB32x8 to HSL32x8
Converts an RGB32 image to an HSL32 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Offset adds an offset to the calculated Hue value when Color Mode is set to HSL. The offset represents the angle by which the hue plane is rotated. Offset can range from 0 to 360. The default offset value of 0 results in a hue value of 0 for the color red (R=255, G=0, B=0). By changing the offset value, you can specify the RGB color that maps to a hue value of 0. When you want to analyze red or colors close to red in the HSL space, you can add an offset so that the hue values associated with these colors are not zero. |
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast RGB32x8 to HSL32x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 17272
- Slice LUTs: 29248
- DSP48s: 96
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 32
- Initiation Interval: 1
IMAQ FPGA Cast HSL32x1 to U1x1
Converts an HSL32 image to a U1 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast HSL32x1 to U1x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 110
- Slice LUTs: 96
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 109
- Slice LUTs: 96
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 110
- Slice LUTs: 94
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 115
- Slice LUTs: 106
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast HSL32x8 to U1x8
Converts an HSL32 image to a U1 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast HSL32x8 to U1x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 470
- Slice LUTs: 378
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast HSL32x1 to U8x1
Converts an HSL32 image to a U8 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast HSL32x1 to U8x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 131
- Slice LUTs: 108
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 130
- Slice LUTs: 106
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 131
- Slice LUTs: 97
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 339
- Slice LUTs: 276
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast HSL32x8 to U8x8
Converts an HSL32 image to a U8 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast HSL32x8 to U8x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 638
- Slice LUTs: 414
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast HSL32x1 to U16x1
Converts an HSL32 image to a U16 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast HSL32x1 to U16x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 139
- Slice LUTs: 119
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 138
- Slice LUTs: 118
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 139
- Slice LUTs: 102
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 144
- Slice LUTs: 115
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast HSL32x8 to U16x8
Converts an HSL32 image to a U16 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast HSL32x8 to U16x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 702
- Slice LUTs: 455
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast HSL32x1 to RGB32x1
Converts an HSL32 image to a RGB32 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast HSL32x1 to RGB32x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 139
- Slice LUTs: 119
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 138
- Slice LUTs: 118
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 139
- Slice LUTs: 102
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 144
- Slice LUTs: 115
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Cast HSL32x8 to RGB32x8
Converts an HSL32 image to a RGB32 image.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Cast HSL32x8 to RGB32x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 139
- Slice LUTs: 119
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 138
- Slice LUTs: 118
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 139
- Slice LUTs: 102
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 144
- Slice LUTs: 115
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1