IMAQ FPGA Binary Morphology VI
- Updated2023-02-21
- 108 minute(s) read
Requires: NI Vision Development Module FPGA
Performs primary morphological transformations.
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Note
This VI has variable latency, which is dependent on the image size. Plug the Minimum Latency value from the Estimated Performance section into the following formula to determine the total latency. For the Erosion and Dilation x1 VI instances, use this formula to calculate the total latency.
For the Open and Close VI x1 instances, use this formula to calculate the total latency.
For the Erosion and Dilation x8 VI instances, use this formula to calculate the total latency.
For the Open and Close x8 VI instances, use this formula to calculate the total latency.
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IMAQ FPGA BinaryMorphology Erosion 3x3
Performs an erosion, which eliminates isolated background pixels.
Supported Image Types
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Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
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Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
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 |
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
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Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
 |
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Erosion 3x3 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 805
- Slice LUTs: 976
- DSP48s: 0
- Block RAMs: 2
Estimated Performance
- Minimum Latency: 9
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 817
- Slice LUTs: 876
- DSP48s: 0
- Block RAMs: 2
Estimated Performance
- Minimum Latency: 9
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 956
- Slice LUTs: 962
- DSP48s: 0
- Block RAMs: 2
Estimated Performance
- Minimum Latency: 8
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 1237
- Slice LUTs: 1043
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 8
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Erosion 3x3 x8
Performs an erosion, which eliminates isolated background pixels.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Erosion 3x3 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 866
- Slice LUTs: 787
- DSP48s: 0
- Block RAMs: 2
Estimated Performance
- Minimum Latency: 8
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Dilation 3x3
Performs a dilation, which eliminates holes isolated in particles.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Dilation 3x3 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 604
- Slice LUTs: 648
- DSP48s: 0
- Block RAMs: 2
Estimated Performance
- Minimum Latency: 9
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 612
- Slice LUTs: 650
- DSP48s: 0
- Block RAMs: 2
Estimated Performance
- Minimum Latency: 9
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 424
- Slice LUTs: 283
- DSP48s: 0
- Block RAMs: 2
Estimated Performance
- Minimum Latency: 8
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 1223
- Slice LUTs: 1039
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 8
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Dilation 3x3 x8
Performs a dilation, which eliminates holes isolated in particles.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Dilation 3x3 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 866
- Slice LUTs: 799
- DSP48s: 0
- Block RAMs: 2
Estimated Performance
- Minimum Latency: 8
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Open 3x3
Performs an erosion followed by a dilation.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Open 3x3 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 1276
- Slice LUTs: 1512
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 17
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 1288
- Slice LUTs: 1418
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 17
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 1421
- Slice LUTs: 1363
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 15
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 2152
- Slice LUTs: 1667
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 15
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Open 3x3 x8
Performs an erosion followed by a dilation.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Open 3x3 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 1491
- Slice LUTs: 1402
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 15
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Close 3x3
Performs a dilation followed by an erosion.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Close 3x3 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 1276
- Slice LUTs: 1513
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 17
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 1276
- Slice LUTs: 1409
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 17
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 1421
- Slice LUTs: 1325
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 15
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 2152
- Slice LUTs: 1673
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 15
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Close 3x3 x8
Performs a dilation followed by an erosion.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Close 3x3 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 1491
- Slice LUTs: 1402
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 15
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Erosion 5x5
Performs an erosion, which eliminates isolated background pixels.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Erosion 5x5 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 1464
- Slice LUTs: 1540
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 9
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 1474
- Slice LUTs: 1585
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 9
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 1431
- Slice LUTs: 1181
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 8
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 1575
- Slice LUTs: 1308
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 8
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Erosion 5x5 x8
Performs an erosion, which eliminates isolated background pixels.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Erosion 5x5 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 1266
- Slice LUTs: 1131
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 9
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Dilation 5x5
Performs a dilation, which eliminates holes isolated in particles.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Dilation 5x5 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 891
- Slice LUTs: 797
- DSP48s: 0
- Block RAMs: 2
Estimated Performance
- Minimum Latency: 9
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 897
- Slice LUTs: 844
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 9
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 761
- Slice LUTs: 569
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 8
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 1575
- Slice LUTs: 1294
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 8
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Dilation 5x5 x8
Performs a dilation, which eliminates holes isolated in particles.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Dilation 5x5 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 1266
- Slice LUTs: 1131
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 9
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Open 5x5
Performs an erosion followed by a dilation.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Open 5x5 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 2163
- Slice LUTs: 2193
- DSP48s: 0
- Block RAMs: 4
Estimated Performance
- Minimum Latency: 17
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 2164
- Slice LUTs: 2165
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 17
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 1648
- Slice LUTs: 1215
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 15
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 2689
- Slice LUTs: 2152
- DSP48s: 0
- Block RAMs: 12
Estimated Performance
- Minimum Latency: 15
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Open 5x5 x8
Performs an erosion followed by a dilation.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Open 5x5 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 2192
- Slice LUTs: 2004
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 17
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Close 5x5
Performs a dilation followed by an erosion.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Close 5x5 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 2163
- Slice LUTs: 2192
- DSP48s: 0
- Block RAMs: 4
Estimated Performance
- Minimum Latency: 17
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 2162
- Slice LUTs: 2142
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 17
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 1648
- Slice LUTs: 1241
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 15
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 2689
- Slice LUTs: 2141
- DSP48s: 0
- Block RAMs: 12
Estimated Performance
- Minimum Latency: 15
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Close 5x5 x8
Performs a dilation followed by an erosion.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Close 5x5 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 2192
- Slice LUTs: 1996
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 17
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Erosion 7x7
Performs an erosion, which eliminates isolated background pixels.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Erosion 7x7 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 1298
- Slice LUTs: 1041
- DSP48s: 0
- Block RAMs: 2
Estimated Performance
- Minimum Latency: 10
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 1295
- Slice LUTs: 1071
- DSP48s: 0
- Block RAMs: 5
Estimated Performance
- Minimum Latency: 10
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 1055
- Slice LUTs: 805
- DSP48s: 0
- Block RAMs: 4
Estimated Performance
- Minimum Latency: 8
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 1109
- Slice LUTs: 898
- DSP48s: 0
- Block RAMs: 5
Estimated Performance
- Minimum Latency: 8
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Erosion 7x7 x8
Performs an erosion, which eliminates isolated background pixels.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Erosion 7x7 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 1713
- Slice LUTs: 1591
- DSP48s: 0
- Block RAMs: 5
Estimated Performance
- Minimum Latency: 9
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Dilation 7x7
Performs a dilation, which eliminates holes isolated in particles.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Dilation 7x7 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 1292
- Slice LUTs: 1007
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 9
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 1289
- Slice LUTs: 1006
- DSP48s: 0
- Block RAMs: 5
Estimated Performance
- Minimum Latency: 9
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 1055
- Slice LUTs: 732
- DSP48s: 0
- Block RAMs: 4
Estimated Performance
- Minimum Latency: 8
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 1109
- Slice LUTs: 885
- DSP48s: 0
- Block RAMs: 5
Estimated Performance
- Minimum Latency: 8
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Dilation 7x7 x8
Performs a dilation, which eliminates holes isolated in particles.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Dilation 7x7 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 1713
- Slice LUTs: 1603
- DSP48s: 0
- Block RAMs: 5
Estimated Performance
- Minimum Latency: 9
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Open 7x7
Performs an erosion followed by a dilation.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Open 7x7 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 2224
- Slice LUTs: 1827
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 18
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 2220
- Slice LUTs: 1956
- DSP48s: 0
- Block RAMs: 9
Estimated Performance
- Minimum Latency: 18
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 1734
- Slice LUTs: 1240
- DSP48s: 0
- Block RAMs: 9
Estimated Performance
- Minimum Latency: 15
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 1788
- Slice LUTs: 1405
- DSP48s: 0
- Block RAMs: 9
Estimated Performance
- Minimum Latency: 15
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Open 7x7 x8
Performs an erosion followed by a dilation.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Open 7x7 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 2898
- Slice LUTs: 2740
- DSP48s: 0
- Block RAMs: 9
Estimated Performance
- Minimum Latency: 17
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Close 7x7
Performs a dilation followed by an erosion.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Close 7x7 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 2224
- Slice LUTs: 1829
- DSP48s: 0
- Block RAMs: 9
Estimated Performance
- Minimum Latency: 18
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 2218
- Slice LUTs: 1880
- DSP48s: 0
- Block RAMs: 9
Estimated Performance
- Minimum Latency: 18
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 1734
- Slice LUTs: 1234
- DSP48s: 0
- Block RAMs: 9
Estimated Performance
- Minimum Latency: 15
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 1788
- Slice LUTs: 1408
- DSP48s: 0
- Block RAMs: 9
Estimated Performance
- Minimum Latency: 15
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Close 7x7 x8
Performs a dilation followed by an erosion.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Close 7x7 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 2898
- Slice LUTs: 2726
- DSP48s: 0
- Block RAMs: 9
Estimated Performance
- Minimum Latency: 17
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Erosion 9x9
Performs an erosion, which eliminates isolated background pixels.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Erosion 9x9 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 1614
- Slice LUTs: 1278
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 10
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 1610
- Slice LUTs: 1428
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 10
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 1322
- Slice LUTs: 913
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 8
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 344
- Slice LUTs: 261
- DSP48s: 0
- Block RAMs: 2
Estimated Performance
- Minimum Latency: 8
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Erosion 9x9 x8
Performs an erosion, which eliminates isolated background pixels.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Erosion 9x9 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 2077
- Slice LUTs: 1965
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 9
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Dilation 9x9
Performs a dilation, which eliminates holes isolated in particles.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Dilation 9x9 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 1614
- Slice LUTs: 1199
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 10
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 1610
- Slice LUTs: 1354
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 10
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 1290
- Slice LUTs: 887
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 8
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 336
- Slice LUTs: 254
- DSP48s: 0
- Block RAMs: 2
Estimated Performance
- Minimum Latency: 8
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Dilation 9x9 x8
Performs a dilation, which eliminates holes isolated in particles.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Dilation 9x9 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 2077
- Slice LUTs: 1948
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 9
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Open 9x9
Performs an erosion followed by a dilation.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Open 9x9 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 2798
- Slice LUTs: 2214
- DSP48s: 0
- Block RAMs: 10
Estimated Performance
- Minimum Latency: 19
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 2792
- Slice LUTs: 2544
- DSP48s: 0
- Block RAMs: 12
Estimated Performance
- Minimum Latency: 19
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 2173
- Slice LUTs: 1528
- DSP48s: 0
- Block RAMs: 12
Estimated Performance
- Minimum Latency: 15
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 556
- Slice LUTs: 414
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 15
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Open 9x9 x8
Performs an erosion followed by a dilation.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Open 9x9 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 3566
- Slice LUTs: 3381
- DSP48s: 0
- Block RAMs: 12
Estimated Performance
- Minimum Latency: 17
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Close 9x9
Performs a dilation followed by an erosion.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Close 9x9 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 2798
- Slice LUTs: 2220
- DSP48s: 0
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 19
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 2794
- Slice LUTs: 2635
- DSP48s: 0
- Block RAMs: 12
Estimated Performance
- Minimum Latency: 19
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 2173
- Slice LUTs: 1505
- DSP48s: 0
- Block RAMs: 12
Estimated Performance
- Minimum Latency: 15
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 556
- Slice LUTs: 414
- DSP48s: 0
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 15
- Initiation Interval: 1
IMAQ FPGA BinaryMorphology Close 9x9 x8
Performs a dilation followed by an erosion.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Structural Element contains the structuring element to apply to the image. The Structural Element matrix should be transposed and then converted to a 1D array before being passed to the VI. For example:
Transpose to:
Convert to 1D array:
|
|||||||||||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
|||||||||||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
|||||||||||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
|||||||||||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
|||||||||||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BinaryMorphology Close 9x9 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 3566
- Slice LUTs: 3459
- DSP48s: 0
- Block RAMs: 12
Estimated Performance
- Minimum Latency: 17
- Initiation Interval: 1