IMAQ FPGA BCGLookup VI
- Updated2023-02-21
- 10 minute(s) read
Requires: NI Vision Development Module FPGA
Applies a brightness, contrast, and gamma correction to an image. The correction is performed by computing and applying a lookup table. Brightness, Contrast, and Gamma control the changes made to the transfer function represented by the lookup table.
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Note
The x8 VI instance has variable latency. Plug the Minimum Latency value from the Estimated Performance section into the following formula to determine the total latency. Total Latency = Minimum Latency + 257 |
IMAQ FPGA BCGLookup U8 x1
Applies a brightness, contrast, and gamma correction to an image. The correction is performed by computing and applying a lookup table. Brightness, Contrast, and Gamma control the changes made to the transfer function represented by the lookup table.
Supported Image Types

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Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
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BCG Values is a cluster of the brightness, contrast, and gamma values.
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Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
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Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
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Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
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Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
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IMAQ FPGA BCGLookup U8 x1 Details
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Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 6335
- Slice LUTs: 7956
- DSP48s: 12
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 67
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 6234
- Slice LUTs: 7350
- DSP48s: 14
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 67
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 6713
- Slice LUTs: 6783
- DSP48s: 12
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 51
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 4303
- Slice LUTs: 6780
- DSP48s: 10
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 51
- Initiation Interval: 1
IMAQ FPGA BCGLookup U8 x8
Applies a brightness, contrast, and gamma correction to an image. The correction is performed by computing and applying a lookup table. Brightness, Contrast, and Gamma control the changes made to the transfer function represented by the lookup table.
Supported Image Types

![]() |
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
![]() |
BCG Values is a cluster of the brightness, contrast, and gamma values.
|
||||||||||
![]() |
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
![]() |
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
![]() |
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
![]() |
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
![]() |
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BCGLookup U8 x8 Details
![]() |
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 25558
- Slice LUTs: 8843
- DSP48s: 12
- Block RAMs: 4
Estimated Performance
- Minimum Latency: 61
- Initiation Interval: 1










