IMAQ FPGA Bayer To RGB VI
- Updated2023-02-21
- 18 minute(s) read
Requires: NI Vision Development Module FPGA
Decodes a Bayer-encoded image to produce an RGB representation of the image. Because the bilinear algorithm is faster, it is recommended to try the bilinear algorithm before the VNG algorithm. If the image contains many edges, or if the quality of edges in the image is important, use the VNG algorithm.
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Note
The VNG VI instance has variable latency, which is dependent on the image size. Plug the Minimum Latency value from the Estimated Performance section into the following formula to determine the total latency. Total Latency = Minimum Latency + (Image Width+2)((Kernel Size/2) - 0.5) + 3 |
IMAQ FPGA BayerToRGB32 Bilinear U8x1
Decodes a Bayer-encoded image to produce an RGB representation of the image using bilinear interpolation to compute pixel values.
Supported Image Types
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Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
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Bayer Parameters specifies the Bayer settings to use to create the image.
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Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
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Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
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Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
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Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
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Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
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IMAQ FPGA BayerToRGB32 Bilinear U8x1 Details
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Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 1448
- Slice LUTs: 1611
- DSP48s: 3
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 11
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 1431
- Slice LUTs: 1462
- DSP48s: 3
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 11
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 1809
- Slice LUTs: 1504
- DSP48s: 3
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 9
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 1786
- Slice LUTs: 1464
- DSP48s: 3
- Block RAMs: 3
Estimated Performance
- Minimum Latency: 9
- Initiation Interval: 1
IMAQ FPGA BayerToRGB32 Bilinear U8x8
Decodes a Bayer-encoded image to produce an RGB representation of the image using bilinear interpolation to compute pixel values.
Supported Image Types
![]() |
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
![]() |
Bayer Parameters specifies the Bayer settings to use to create the image.
|
||||||||||||||||||
![]() |
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
![]() |
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
![]() |
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
![]() |
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
![]() |
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BayerToRGB32 Bilinear U8x8 Details
![]() |
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 5240
- Slice LUTs: 3749
- DSP48s: 24
- Block RAMs: 5
Estimated Performance
- Minimum Latency: 14
- Initiation Interval: 1
IMAQ FPGA BayerToRGB32 VNG U8x1
Decodes a Bayer-encoded image to produce an RGB representation of the image using variable number of gradients (VNG) interpolation to compute pixel values.
Supported Image Types
![]() |
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
![]() |
Bayer Parameters specifies the Bayer settings to use to create the image.
|
||||||||||||||||||
![]() |
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
![]() |
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
![]() |
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
![]() |
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
![]() |
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BayerToRGB32 VNG U8x1 Details
![]() |
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 4461
- Slice LUTs: 5686
- DSP48s: 19
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 16
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 4566
- Slice LUTs: 5429
- DSP48s: 19
- Block RAMs: 12
Estimated Performance
- Minimum Latency: 16
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 3880
- Slice LUTs: 4926
- DSP48s: 19
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 20
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 3270
- Slice LUTs: 4533
- DSP48s: 19
- Block RAMs: 6
Estimated Performance
- Minimum Latency: 20
- Initiation Interval: 1
IMAQ FPGA BayerToRGB32 VNG U8x8
Decodes a Bayer-encoded image to produce an RGB representation of the image using variable number of gradients (VNG) interpolation to compute pixel values.
Supported Image Types
![]() |
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
![]() |
Bayer Parameters specifies the Bayer settings to use to create the image.
|
||||||||||||||||||
![]() |
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
![]() |
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
![]() |
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
![]() |
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
![]() |
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA BayerToRGB32 VNG U8x8 Details
![]() |
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 28511
- Slice LUTs: 34949
- DSP48s: 168
- Block RAMs: 9
Estimated Performance
- Minimum Latency: 29
- Initiation Interval: 1