IMAQ FPGA Absolute Difference VI
- Updated2023-02-21
- 67 minute(s) read
Requires: NI Vision Development Module FPGA
Subtracts one image from another or a constant from an image and returns the absolute value of the difference.
IMAQ FPGA Absolute Difference U8 x1
Subtracts one image from another image and returns the absolute value of the difference.
Supported Image Types
 |
Pixel Bus In A when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
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Pixel Bus In B when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
 |
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
 |
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
 |
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Absolute Difference U8 x1 Details
 |
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 159
- Slice LUTs: 144
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 160
- Slice LUTs: 136
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 159
- Slice LUTs: 137
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 160
- Slice LUTs: 128
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Absolute Difference U8 x8
Subtracts one image from another image and returns the absolute value of the difference.
Supported Image Types
|
Pixel Bus In A when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Pixel Bus In B when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Absolute Difference U8 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 494
- Slice LUTs: 503
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Absolute Difference U16 x1
Subtracts one image from another image and returns the absolute value of the difference.
Supported Image Types
|
Pixel Bus In A when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Pixel Bus In B when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Absolute Difference U16 x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 206
- Slice LUTs: 202
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 205
- Slice LUTs: 175
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 206
- Slice LUTs: 201
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 206
- Slice LUTs: 194
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Absolute Difference U16 x8
Subtracts one image from another image and returns the absolute value of the difference.
Supported Image Types
|
Pixel Bus In A when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Pixel Bus In B when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Absolute Difference U16 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 820
- Slice LUTs: 848
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Absolute Difference RGB32 x1
Subtracts one image from another image and returns the absolute value of the difference.
Supported Image Types
|
Pixel Bus In A when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Pixel Bus In B when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Absolute Difference RGB32 x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 286
- Slice LUTs: 255
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 285
- Slice LUTs: 219
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 216
- Slice LUTs: 191
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 286
- Slice LUTs: 264
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Absolute Difference RGB32 x8
Subtracts one image from another image and returns the absolute value of the difference.
Supported Image Types
|
Pixel Bus In A when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Pixel Bus In B when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Absolute Difference RGB32 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 1528
- Slice LUTs: 1398
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Absolute Difference HSL32 x1
Subtracts one image from another image and returns the absolute value of the difference.
Supported Image Types
|
Pixel Bus In A when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Pixel Bus In B when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Absolute Difference HSL32 x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 286
- Slice LUTs: 255
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 285
- Slice LUTs: 220
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 216
- Slice LUTs: 191
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 286
- Slice LUTs: 263
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Absolute Difference HSL32 x8
Subtracts one image from another image and returns the absolute value of the difference.
Supported Image Types
|
Pixel Bus In A when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Pixel Bus In B when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
IMAQ FPGA Absolute Difference HSL32 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 1528
- Slice LUTs: 1397
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Absolute Difference with Constant U8 x1
Subtracts a constant from an image and returns the absolute value of the difference.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
 |
Constant is the value used for image-constant operations. The default is 0. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
IMAQ FPGA Absolute Difference with Constant U8 x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 144
- Slice LUTs: 159
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 145
- Slice LUTs: 178
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 144
- Slice LUTs: 156
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 144
- Slice LUTs: 143
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Absolute Difference with Constant U8 x8
Subtracts a constant from an image and returns the absolute value of the difference.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Constant is the value used for image-constant operations. The default is 0. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
IMAQ FPGA Absolute Difference with Constant U8 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 416
- Slice LUTs: 670
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Absolute Difference with Constant U16 x1
Subtracts a constant from an image and returns the absolute value of the difference.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
 |
Constant is the value used for image-constant operations. The default is 0. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
IMAQ FPGA Absolute Difference with Constant U16 x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 192
- Slice LUTs: 224
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 191
- Slice LUTs: 243
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 191
- Slice LUTs: 210
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 191
- Slice LUTs: 220
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Absolute Difference with Constant U16 x8
Subtracts a constant from an image and returns the absolute value of the difference.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Constant is the value used for image-constant operations. The default is 0. |
||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
IMAQ FPGA Absolute Difference with Constant U16 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 686
- Slice LUTs: 1037
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Absolute Difference with Constant RGB32 x1
Subtracts a constant from an image and returns the absolute value of the difference.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
 |
Constant is the value used for image-constant operations. The default is 0.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
IMAQ FPGA Absolute Difference with Constant RGB32 x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 267
- Slice LUTs: 271
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 266
- Slice LUTs: 256
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 197
- Slice LUTs: 189
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 267
- Slice LUTs: 254
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Absolute Difference with Constant RGB32 x8
Subtracts a constant from an image and returns the absolute value of the difference.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Constant is the value used for image-constant operations. The default is 0.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
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|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
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|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
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|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
IMAQ FPGA Absolute Difference with Constant RGB32 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 1294
- Slice LUTs: 1891
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Absolute Difference with Constant HSL32 x1
Subtracts a constant from an image and returns the absolute value of the difference.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Constant is the value used for image-constant operations. The default is 0.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
IMAQ FPGA Absolute Difference with Constant HSL32 x1 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Virtex-5
Estimated Device Utilization
- Slice Registers: 267
- Slice LUTs: 271
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Spartan-6
Estimated Device Utilization
- Slice Registers: 266
- Slice LUTs: 256
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Zynq
Estimated Device Utilization
- Slice Registers: 197
- Slice LUTs: 189
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
Kintex-7
Estimated Device Utilization
- Slice Registers: 267
- Slice LUTs: 254
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1
IMAQ FPGA Absolute Difference with Constant HSL32 x8
Subtracts a constant from an image and returns the absolute value of the difference.
Supported Image Types
|
Pixel Bus In when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Constant is the value used for image-constant operations. The default is 0.
|
||||||||||||||||||
|
Input Valid specifies whether the next data point has arrived for processing. Wire the Output Valid output of an upstream node to this input to transfer data from the upstream node to this node. |
||||||||||||||||||
|
Ready For Output specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the Ready for Input output of a downstream node to this input of the current node.
|
||||||||||||||||||
|
Pixel Bus Out when Input Valid is TRUE, contains one of the following: valid pixel data, an end of line signal, or an end of image signal.
|
||||||||||||||||||
|
Ready for Input returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the Ready for Output input of an upstream node.
|
||||||||||||||||||
|
Output Valid returns TRUE if this node has computed a result that downstream nodes can use. Wire this output to the Input Valid input of a downstream node to transfer data from the node to the downstream node. |
IMAQ FPGA Absolute Difference with Constant HSL32 x8 Details
|
Note Resource estimates are based on a 40 MHz clock. |
Kintex-7
Estimated Device Utilization
- Slice Registers: 1294
- Slice LUTs: 1890
- DSP48s: 0
- Block RAMs: 0
Estimated Performance
- Minimum Latency: 1
- Initiation Interval: 1