Synchronization Overview for USRP RIO Devices Using LabVIEW FPGA

Synchronization coordinates Data Clock cycles across multiple USRP RIO devices. Sources of error, such as common clock propagation delay, cabling and cable lengths, analog delays in the FPGA, and skew/jitter in the common clock, can affect frequency and phase relationships among devices.

Use the programming example to synchronize across multiple USRP RIO devices.

Synchronization aligns the devices so that the devices are synchronized to the nearest Data Clock cycle. The devices may be offset by up to one half of one Data Clock cycle if the devices are ±180 degrees out of phase. If the devices are zero degrees out of phase, device alignment offset is zero degrees.

Note For the best synchronization results, minimize the phase offset of the Data Clocks.

Before attempting to synchronize your USRP RIO devices, notice the following caveats:

  • Synchronization does not account for differences in analog signal paths.
  • Synchronization does not account for data pipeline delays that occur before and after the synchronization VIs. For example, synchronization does not account for ADC/DAC pipeline delays.
  • The synchronized edge is always delayed relative to the unsynchronized edge. The application is responsible for accounting for this delay, if necessary. The synchronization VIs provide the actual synchronization delay value.
  • You must lock all devices to a common time reference. Use the Reference Clock as the time reference.
  • You must set the synchronization registers for the Reference Clock to zero.
  • Synchronization does not account for propagation delays of the Reference Clock.
  • All Data Clocks must have a fixed phase relationship with each other.
  • The Common Periodic Time Reference (CPTR) period must be greater than the maximum propagation delay of a signal from the master device to any slave device across the selected FPGA I/O line.
  • The CPTR period must be the same across all devices.
  • You must route the FPGA I/O lines to all the devices that you are synchronizing.

Methods of Synchronization

The synchronization library provides two alignment methods—FPGA self-synchronization and host-driven synchronization. Both synchronization methods produce the same quality of synchronization, but differ in their requirements and versatility of operation. Select the alignment method that best fits your needs.

FPGA Self-Synchronization

FPGA self-synchronization does not require host involvement. Use of the host VIs is optional. The FPGAs can all independently align their CPTRs. To perform a self-synchronization, your devices must meet the following requirements:

  • Data Clocks are locked to the same Reference Clock.
  • Data Clocks are an integer multiple of the Reference Clock.
  • All the devices are fewer than 90 degrees out of phase with each other.
Note FPGA self-synchronization is repeatable only if the devices meet all the requirements. If the devices do not meet all requirements, use host-driven synchronization.

Host-Driven Synchronization

Host-driven synchronization allows you to perform the following actions:

  • Decouple the Data Clock and the Reference Clock
  • Use an external Data Clock
  • Set the CPTR period manually
  • Synchronize repeatedly

Host-driven synchronization requires an additional FPGA I/O line and host involvement for CPTR alignment.

Note Host-driven synchronization is repeatable only if the phase relationships between devices remain constant.

Host-driven synchronization guarantees that the maximum phase offset between the master and slave device is one-half of a Data Clock period. The phase offset approaches zero as the phase relationships between the devices approach zero.

Note The phase relationship between the device and the Reference Clock does not affect host-driven synchronization.

Topologies for Synchronization

The synchronization library provides support for two topologies—a bus topology and a star topology. Both topologies produce the same quality of synchronization, but differ in their physical cabling and connection requirements. Select the topology that best fits your needs.

Bus Topology

A bus topology uses a single, common backbone to connect all devices. A bus topology requires that the I/O serves both input and output signals from the same line. For USRP RIO devices, this line is the AUX I/O front panel connector.

To configure a bus topology, connect all the devices you want to synchronize using a common AUX I/O connection. Use the Synchronize over AUX I/O VI on the FPGA. You can devote individual AUX I/O lines to each signal that you want to synchronize.

Star Topology

A star topology uses the output of a single device to connect to the input of all other devices. A star topology assumes there are separate lines for input and output. For USRP RIO devices, these lines are the PPS TRIG IN and PPS TRIG OUT rear panel connectors.

To configure a star topology, wire the PPS TRIG OUT connector of one device to its own PPS TRIG IN connector and to the PPS TRIG IN connectors of the other devices you want to synchronize. Use the Synchronize over PPS TRIG VI on the FPGA. Because all synchronization signals pass over this single I/O line, you must take additional care to ensure that only one signal at a time is synchronized.

This topology requires another device to route Reference Clocks and triggers to the device. Consider the PXIe-6674T Synchronization Module or the CDA-2990 Clock Distribution Device.

Note You can find examples of both FPGA code and host code for synchronization in the NI-USRP sample projects. You can open the sample projects in LabVIEW by selecting File » Create Projects » NI-USRP.

How Synchronization Works

When you share triggers among multiple devices, propagation delays on the signal path cause triggers to arrive at different times on each device. The synchronization library uses the CPTR to slow down the trigger evaluation rate. All devices must produce a CPTR signal that is equal in frequency and phase-aligned.

The synchronization FPGA VIs produce and align a CPTR that occurs simultaneously across all the FPGAs. The CPTR is periodic, and the Data Clock rate controls the CPTR period. When you power on the FPGAs, the CPTRs are not aligned. The alignment FPGA VI and the host VI align the CPTRs. The following figure shows the relationship among the CPTRs, the Reference Clock, and the Data Clock.

Figure 7. CPTR Alignment

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Note Lock Device A and Device B to a common clock.

After the CPTRs are aligned, synchronize an edge across multiple FPGAs. The master device distributes the signal across an FPGA I/O line. All devices monitor the same FPGA I/O line. The edge is synchronized at the next CPTR edge. After all the device CPTRs are aligned, an edge sent out on the FPGA I/O lines is read at the same clock cycle across all the devices.

Note The quality of synchronization is only as good as the quality of Data Clock locking. Some static skew may exist. You can calibrate to eliminate this skew if necessary.

The following figure shows the relationship between the time that the master device reads a Reference Trigger (Ref Trig) and the time that all the devices read the synchronized version of the Reference Trigger (Synchronized Ref Trig). This synchronization requires CPTR alignment on all the devices.

Figure 8. Reading the Reference Triggers

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Synchronization Checklist

Verify that the settings in the system, the project, the host VI, and the FPGA VI are configured as follows.

  • System settings:
    • Route or connect all signals used in synchronization. Connect the SMA cables for the PPS TRIG IN connector, the PPS TRIG OUT connector, or the AUX I/O connector.
  • Project settings:
    • Add the FPGA Reference Clock.
    • Configure the Reference Clock to have zero synchronization registers. In the FPGA IO Property dialog box, set Number of Synchronization Registers for Read to 0.
    • Add the FPGA I/O lines that you are synchronizing. Do not remove synchronization registers.
  • Host VI:
    • Configure the clock source based on the project settings.
    • Lock the clock to the clock source.
    • Run the Synchronization VI.
    • Refer to the example FPGA code in the NI-USRP sample projects. You can open the sample projects in LabVIEW by selecting File » Create Project » NI-USRP.
  • FPGA VI:
    • Configure the CPTR period. The synchronization library ensures that the CPTR period is the same on the host and the FPGA.