Instruction Synchronizer Overview for USRP RIO Devices Using LabVIEW FPGA

Use this instrument design library (IDL) to issue instructions instantaneously to multiple FPGA subsystems on one or more devices.

The Instruction Synchronizer IDL can be triggered from the Time or Sync IDLs or through a user-defined method. The Instruction Synchronizer IDL is used in the USRP-2945/2955 sample project to achieve phase synchronization by sending the tuning commands to each radio register subsystem at the same time.

Instruction Synchronization Subsystem

The Instruction Synchronization subsystem is immediately upstream of the subsystem to be synchronized, between it and the rest of the register bus. The instruction synchronizer can be commanded to capture and store instructions intended for the attached subsystem in an internal first-in-first-out memory buffer (FIFO); later, the captured instructions can be issued after the instruction synchronizer receives a trigger. Any additional instruction synchronizers that receive the same trigger will also begin to issue their instructions on the same clock cycle.

Programming

  • Each subsystem to be synchronized requires a dedicated instruction synchronizer.
  • Only write instructions are supported. Read instruction cannot be synchronized.
  • Subsystems that are to be synchronized with each other must have their instruction synchronizers driven by the same trigger.

Using Instruction Synchronization

The Instruction Synchronizer IDL includes the host and FPGA VIs necessary for synchronization.

FPGA

  1. Place the Instruction Synchronizer VI directly upstream of the subsystem to be synchronized.
  2. Connect the register instruction input of the subsystem to be synchronized to the register instruction out output of the synchronizer.
  3. Connect the trigger input of the synchronizer to any rising edge pulse source, such as one of the following:
    • Time IDL's Future Time Event
    • Sync IDL's Synchronize Signal Bus or Synchronize over PPS Trig
    • FPGA control

Host

Complete the following steps on the host side to use the synchronizers:

  1. Wire the Reset VI before wiring any other Instruction Synchronizer IDL VI.
  2. Wire the Queue Instructions VI with any instructions you wish to have synchronized.
  3. Once all instructions that need to be synchronized have been queued in the synchronizers, use the Set Trigger Enabled VI to enable the synchronizers to be to triggered.
Note The Public IDL VI are meant for the register bus setup as used in the sample project. If you are creating a custom project with one or more different register buses, you will need to use the Advanced VIs to send commands to the correct register bus.