FPGA Self Synchronization
- Updated2023-02-17
- 3 minute(s) read
FPGA Self Synchronization
Use this type of synchronization in conjunction with FPGA Align on the FPGA. Refer to the FPGA nodes for documentation. When this node finishes, the FPGAs are synchronized.
Inputs/Outputs
niusrprio sessions in
Objects created by the Open node and used as the session handles for the USRP RIO nodes.
error in
Error conditions that occur before this node runs.
The node responds to this input according to standard error behavior.
Default value: No error
sync.cptr.period
The period (in clocks) of the common periodic time reference (CPTR).
The CPTR period controls the rate at which synchronized signals are realized. This parameter is required, and there must be a value for each device participating in synchronization. When you use FPGA Align, the CPTR period must be the same as the Reference Clock period. The sync.cptr.period must be set to the ratio of the clock-driven loop (CDL) rate (that the Align node is in) to the
common reference rate. For example, the CPTR period must be 12 if you use the GPS for the Reference Clock, and the Data Clock for the CDL Clock (120 MHz/10 MHz). When you use Host Align, this value is configurable. The maximum value is 63. The minimum value for the sync.cptr.period must be big enough to ensure transmission across the
sync.fpga io line. Refer to the specifications for the FPGA I/O line chosen. For example, if the FPGA I/O line has a maximum propagation delay of 50 ns, the minimum value would be 6. Because the period of the 120 MHz Data Clock is ~8.333 ns, it would require 6 clocks to exceed 50 ns. NI does not recommend changing the CPTR period while running. You must re-run alignment if you change the CPTR period.
niusrprio sessions out
niUsrpRio sessions used in all subsequent USRP RIO host nodes.
error out
Error information.
The node produces this output according to standard error behavior.