Host Align Bus
- Updated2023-02-17
- 2 minute(s) read
Host Align Bus
Aligns the participating targets connected to a common bus, typically AUX I/O, before synchronizing a signal.
Inputs/Outputs
sync.resources in
Synchronization instance. sync.resources is obtained from the Create node.
common reference
The "start" signal used by the measurement logic.
When you use the FPGA Align node, the common reference must be the same clock to which the FPGA clock of the target is locked.
clock x2
Measurement clock used by the measurement logic.
This clock must run at twice the rate of the FPGA Clock, which is the clock that drives the clock-driven loop (CDL) that this node is in. This clock must also derive from the FPGA Clock so that it has a fixed phase relationship. This clock is commonly Data Clock x2.
sync.meas.fpga io
The FPGA I/O line to send and receive the measurement signals on. This line is commonly an AUX I/O line.
sync.resources out
The same instance that was passed in for sync.resources.