Disconnect Trigger Terminals
- Updated2023-02-17
- 4 minute(s) read
Disconnect Trigger Terminals
Closes a route between a source trigger terminal and a destination trigger terminal.
After you invoke this function, you can use the associated terminal for other operations. You must use this node any time you connect trigger terminals using Connect Trigger Terminals.
Inputs/Outputs
session in
The session that you obtain from Initialize.
error in
Error conditions that occur before this node runs.
The node responds to this input according to standard error behavior.
Default value: No error
source terminal
The source trigger terminal to connect to the destination terminal.
| PXI_Trig<n> | The basic trigger lines of a PXI or PXIe chassis. |
| PXI_Star<n> | The star trigger lines of a PXI or PXIe chassis.
Note Each PXI_Star trigger is mapped to a single slot. This mapping is vendor specific. Refer to the hardware documentation to determine the orientation of PXI_Star lines in the chassis.
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| PFI<n> | The PFI connectors on the front panel of the module. You can use PFI connectors to route triggers between multiple chassis or devices. |
| PFI_LVDS<n> | The PFI low voltage differential signaling (LVDS) input/output connectors on the front panel of your device. Signals on PFI LVDS lines use the standard PFI synchronization clock. |
| Ground | The Ground connector continuously outputs a logic low signal, unless it is inverted. |
| Full Speed Clock | The full speed synchronization clock signal of the destination terminal zone. Use this source to send a full-speed clock signal along a trigger line (for example, to route a PXI_Clk10 clock signal to a PFI line).
Caution Routing a clock signal through a PXI_Trig line is not recommended, due to poor clock signal integrity caused by the topology of the PXI_Trig lines. Use PXI_Star, PXIe_DStar, or PFI lines instead.
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| Divided Clock 1 | The first divided clock signal of the destination terminal zone. This source divides the synchronization clock of the destination terminal by the value you specify in the Clock Divisor 1 parameter of niSync Properties and uses the result as the trigger source. |
| Divided Clock 2 | The second divided clock signal of the destination terminal zone. This source divides the synchronization clock of the destination terminal by the value you specify in the Clock Divisor 2 property of niSync Properties and uses the result as the trigger source. |
| ClkIn | The ClkIn connector on the front panel of the device. Use this terminal to route triggers from an external device. |
| PXIe_DStarC<n> | The differential star trigger lines of the PXIe chassis. Use PXIe_DStarC lines to send trigger and clock signals from a peripheral slot to the system timing slot of the chassis.
Note Each PXIe_DStarC trigger is mapped to a single slot. This mapping is vendor specific. Refer to your chassis documentation to determine the orientation of differential star trigger lines.
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| PXIe_DStarB | The differential star trigger lines of the PXIe chassis. Use PXIe_DStarB lines to send trigger signals from the system timing slot to a peripheral slot of the chassis. |
destination terminal
The destination trigger terminal to which the source terminal connects.
| PXI_Trig<n> | The basic trigger lines of the PXI or PXIe chassis. |
| PXI_Star<n> | The star trigger lines of the PXI or PXIe chassis. Each star trigger line is a dedicated connection between the system timing slot and one other slot. Note Each PXI_Star trigger is mapped to a single slot. This mapping is vendor specific. Refer to the hardware documentation to determine the orientation of PXI_Star lines in the chassis. |
| PFI<n> | The PFI connectors on the front panel of the module. |
| PFI_LVDS<n> | The PFI low voltage differential signaling (LVDS) input/output connectors on the front panel of the module. |
| PXIe_DStarB<n> | The differential star trigger lines of the PXIe chassis. Use PXIe_DStarB lines to send trigger signals from the system timing slot to a peripheral slot of the chassis. Note Each PXIe_DStarB trigger is mapped to a single slot. This mapping is vendor specific. Refer to the chassis documentation to determine the orientation of differential star trigger lines. |
| PXIe_DStarC | The differential star trigger lines of the PXIe chassis. Use PXIe_DStarC lines to send trigger and clock signals from a peripheral slot to the system timing slot of the chassis. |
session out
The session handle for the NI-Sync device. Pass this handle to other NI-Sync nodes to program the behavior of the device.
error out
Error information.
The node produces this output according to standard error behavior.