Connect Software Trigger
- Updated2023-02-17
- 4 minute(s) read
Connect Software Trigger
Connects the global software trigger terminal to a destination trigger terminal.
Once you connect the global software trigger, you can fire the trigger using Send Software Trigger.
Inputs/Outputs
update edge
The synchronization clock update edge on which the connected signal is propagated.
The source and destination terminals must be connected synchronously for this parameter to apply.
| Rising Edge | 0 | Propagates the trigger when the digital signal of the synchronization clock transitions from low to high, i.e. the rising edge. |
| Falling Edge | 1 | Propagates the trigger when the digital signal of the synchronization clock transitions from high to low, i.e. the falling edge. |
Default value: Rising Edge
synchronization clock
The clock to use to synchronize a trigger signal.
| Full Speed Clock | Uses the full speed frequency of the synchronization clock to synchronize the trigger. |
| Divided Clock 1 | Divides the synchronization clock by the value specified in the Clock Divisor 1 property of the niSync Property Node and uses the frequency of the divided clock to synchronize the trigger. |
| Divided Clock 2 | Divides the synchronization clock by the value specified in the Clock Divisor 2 property of the niSync Property Node and uses the frequency of the divided clock to synchronize the trigger. |
Default value: Full Speed Clock
session in
The session that you obtain from Initialize.
error in
Error conditions that occur before this node runs.
The node responds to this input according to standard error behavior.
Default value: No error
source terminal
The source software trigger terminal to connect to the destination terminal.
The only acceptable value is Global Software Trigger.
Default value: Global Software Trigger
destination terminal
The destination trigger terminal that the global software trigger terminal will connect to.
| PXI_Trig<n> | The basic trigger lines of a PXI or PXIe chassis. |
| PXI_Star<n> | The star trigger lines of a PXI or PXIe chassis. Each star trigger line is a dedicated connection between the system timing slot and one other slot.
Note Each PXI_Star trigger is mapped to a single slot. This mapping is vendor specific. Refer to the hardware documentation to determine the orientation of PXI_Star lines in the chassis.
|
| PFI<n> | The PFI connectors on the front panel of the module. |
| PFI_LVDS<n> | The PFI low voltage differential signaling (LVDS) input/output connectors on the front panel of the device. |
| PXIe_DStarB<n> | The differential star trigger lines of the PXIe chassis. Use PXIe_DStarB lines to send trigger signals from the system timing slot to a peripheral slot of the chassis. |
| PXIe_DStarC | The differential star trigger lines of the PXIe chassis. Use PXIe_DStarC lines to send trigger and clock signals from a peripheral slot to the system timing slot of the chassis. |
Default value: PXI_Trig0
invert
A ring value that specifies whether or not to invert the source terminal signal at the destination terminal.
| Don't Invert Signal | 0 | Keeps the digital signal of the source trigger terminal in its original format. |
| Invert Signal | 1 | Inverts the digital signal of the source trigger terminal so that its rising edges are now its falling edges, and vice versa. |
Default value: Don't Invert Signal
delay
The number of seconds to delay the global software trigger pulse.
The delay must be a multiple of the synchronization clock period. The global software trigger can be delayed up to 15 clock cycles for each route.
session out
The session handle that you obtain from Initialize.
error out
Error information.
The node produces this output according to standard error behavior.