NISYNC_ATTR_SYNC_CLK_RST_DDS_CNTR_ON_PXITRIG
- Updated2023-02-21
- 1 minute(s) read
| Data Type |
Access | Applies to | Coercion | High-Level Functions |
|---|---|---|---|---|
| ViBoolean | R/W | N/A | None | None |
Description
Specifies whether or not the DDS clock dividers should reset when the device receives an update pulse on the PXI_Trig line specified in the NISYNC_ATTR_SYNC_CLK_RST_PXITRIG_NUM attribute. If TRUE, the DDS clock dividers reset on the rising edge of the update pulse.
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Note This attribute is supported only on signal-based devices. |