niHSDIO Configure Ref Clock VI
- Updated2023-02-21
- 4 minute(s) read
Configures the Reference clock. Use this VI when you are using the On Board Clock as a Sample clock and you want the Sample clock to be phase-locked to a reference signal. Phase-locking the Sample clock to a Reference clock prevents the Sample clock from losing alignment with the Reference clock. The driver ignores the Reference clock rate input when the Reference clock source is PXI Clock.
Refer to Clocks for Digital Waveform Generator/Analyzers for more information about the Reference clock.
Related Topics

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instrument handle identifies your instrument session. instrument handle is obtained from the niHSDIO Init Acquisition Session VI, the niHSDIO Init Generation Session VI, or the niHSDIO Init Ext Cal VI. |
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source specifies the phase-lock loop (PLL) reference clock source.
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clock rate specifies the Reference clock rate, expressed in Hz. |
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error in (no error) describes error conditions that occur before this node runs. This input provides standard error in functionality.
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instrument handle out passes a reference to your instrument session to the next VI. instrument handle is obtained from the niHSDIO Init Acquisition Session VI or the niHSDIO Init Generation Session VI. |
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error out contains error information. This output provides standard error out functionality.
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