NI-HSDIO Express (Acquisition) VI

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Updated2023-02-21
7 minute(s) read

NI-HSDIO Express (Acquisition) VI (Deprecated)

This VI is deprecated. NI recommends that you use the Dynamic Acquisition with Fetch.vi or Dynamic Acquisition with Read.vi examples instead of this VI as a starting point for new applications you create.

This VI will execute in code created with versions of NI-HSDIO earlier than 19.0, but it cannot be reconfigured from a dialog box with NI-HSDIO 19.0 or later. To reconfigure this VI, right-click the Express VI and select Open Front Panel»Convert. This will convert the Express VI to code that you can configure on the block diagram.

Acquires a digital waveform from a National Instruments digital waveform generator/analyzer.

Note NI 6555/6556 devices are not supported by NI-HSDIO Express VIs.

Block Diagram Inputs

Block Diagram Outputs

Parameter

Description

Configuration

Contains the following options:

Device—Specifies the device to use for the acquisition. This ring control lists all devices installed on this computer which can be used by this Express VI. If you reopen the NI-HSDIO Express (Acquisition) configuration page and the current device is dimmed, the device name has changed or the device is no longer in the system.
Compare Mode—Specifies whether this Express VI compares the acquired data to an expected response. Configure the expected response data source using the Compare Mode tab. This feature is not supported on all devices.
- No Comparison—Disables compare mode.
- HW Compare—Enables the comparison of acquired and expected data on the device (supported only on NI 6547/6548/655x devices).
- SW Compare—Enables the comparison of acquired and expected data on the PC.
Tristate channels before acquisition—Specifies whether configured channels that were previously left generating data are tristated.
Checked: Configured channels previously left generating data are tristated.

Unchecked: Configured channels previously left generating data are not tristated.
Double Data Rate—Specifies whether or not to process data in double data rate (DDR) mode. This feature is not supported on all devices.
Checked: Configures device for DDR mode.

Unchecked: Disables DDR mode.
Channels—Displays the channels currently configured to acquire data.
- Modify—Click Modify to launch the Select Channels dialog box.
Timing—Contains the following options:
- Rate (Hz)—Specifies the Sample clock frequency for the acquisition.
- Samples to read—Specifies the number of samples to acquire.

Voltage

Contains the following options:

Logic family—Specifies the voltage level thresholds for the acquired data to use one of the predefined logic families.
Custom levels (V)—Specifies that the acquisition data use custom-defined voltage levels.
- High—Specifies the high voltage threshold for the acquisition. This feature is not supported on all devices.
- Low—Specifies the low voltage threshold for the acquisition. This feature is not supported on all devices.

Trigger

Configures the trigger options. Contains the following options:

Reference trigger type—Specifies the Reference trigger type for the acquisition.
If this control is set to None, the acquisition starts as soon as you run this VI. For all other values, the VI configures the device to wait for a trigger and returns the number of samples you configure in pretrigger samples immediately before the trigger and returns the remaining samples immediately after the trigger.

If this control is set to Digital Edge, the following options are visible:
- Max Time (s)—Specifies how long to allow the VI to complete the finite acquisition before returning a timeout error. This control is only available in the Finite acquisition mode.
  Units: Seconds (s)
- Pretrigger samples—Specifies the number of Pretrigger samples the device must receive before the Reference trigger is acknowledged. Of the total number of samples returned by the VI, the number of samples configured as pretrigger samples are acquired immediately prior to the trigger. The remaining samples are acquired immediately after the trigger.
- Trigger source—Specifies the trigger source. The digital waveform generator/analyzer waits for the specified trigger to start the acquisition.
- Digital Edge—Specifies whether to trigger on a rising or falling edge of the trigger signal.
If this control is set to Pattern Match, the following options are visible:
- Max Time (s)—Specifies how long to allow the VI to complete the finite acquisition before returning a timeout error. This control is only available in the Finite acquisition mode.
  Units: Seconds (s)
- Pretrigger samples—Specifies the number of Pretrigger samples the device must receive before the Reference trigger is acknowledged. Of the total number of samples returned by the VI, the number of samples configured as Pretrigger samples are acquired immediately prior to the trigger. The remaining samples are acquired immediately after the trigger.
- Pattern—Shows the currently configured pattern that activates the pattern-match trigger under the conditions specified in Trigger when.
  The following list shows the characters you can use in your pattern string.
  
  X = Ignore the channel
  0 = Match on a logic 0
  1 = Match on a logic 1
  R = Match on a rising edge
  F = Match on falling edge
  E = Match on either edge
  
  Push the ... button to the right of the control to edit the pattern.
- Trigger when—Specifies the conditions under which the trigger asserts.
  
  Data Matches Pattern means that the trigger asserts when the sampled pattern matches the pattern specified in pattern.
  
  Data Does Not Match Pattern means that the trigger asserts when the sampled pattern does not match the pattern specified in pattern.

Advanced Timing

Configures options used less frequently for timing. Contains the following options:

Clock Configuration—Contains the following options:

Sample clock source—Specifies the Sample clock source.

Note When On Board Clock is not selected and the clock rate is inaccurate, the driver may return an error. All external clocks must have accurate values for the clock rate input, including Strobe and PXI_STAR Line.

Reference clock source—Specifies the PLL reference clock source. The device phase-locks the Sample clock to the Reference clock signal to prevent the Sample clock from drifting relative to the Reference clock.

Data position—Contains the following options:
- Data position—Specifies which edge of the Sample clock signal is used to acquire each sample. You can also configure the device to acquire data at a configurable delay past each rising edge of the Sample clock.
- Data delay—Specifies the time after the rising edge of the Sample clock before data is acquired. Data delay is expressed as a fraction of the clock period.
Use relative initial time—Specifies if the timestamp value of the output waveform is absolute or relative to the trigger point.
Checked: Timestamp is relative to the trigger point.

Unchecked: Timestamp is absolute.

Compare Mode

Contains the following options:

Expected Response Data—Contains the following options:
- Data Source—Specifies whether the Express VI retrieves the data to generate from an .hws (Hierarchical Waveform Storage) file. Otherwise, data must be wired to the data input terminal.
- Path—If Read from file is selected, use this control to specify the .hws file containing the data to compare.
- Loop Count—Specifies the number of times to repeat the current finite waveform.
Results—Contains the following options:
- BER—Enables bit error rate (BER) calculation. BER is calculated by taking the number of sample errors and dividing it by the total number of samples compared.
- BER per channel—Enables bit error rate (BER) calculations for each configured channel. BER for an individual channel is calculated by taking the number of bit errors found for that channel and dividing it by the total number of samples compared.
- Fault Locations—Enables the retrieval of the locations for the bits that were in error. Only the first 1,024 sample errors are returned.

Block Diagram Inputs

Parameter

Description

data

Contains the expected response data for the comparison operation. data does not exist when you select the Read from File option in the NI-HSDIO Express (Acquisition) configuration page or when HWC is not configured.

close

Determines whether the instrument session remains open when the VI finishes execution. Use this parameter for loop optimization by setting it to FALSE on all iterations other than the last iteration. close is TRUE by default.

Note This input is not intended to be used to share the session between Express VIs. If you have a loop containing multiple Express VIs that use the same device, you must wire in TRUE for this input.

max time

Specifies the timeout value for the Express VI.

error in

Describes error conditions that occur before this Express VI runs.

Block Diagram Outputs

Parameter	Description
data	Contains the digital data acquired by the device.
passed	Returns the pass/fail result of the last hardware comparison operation.
number of sample errors	Returns the number of sample errors found in the last hardware comparison operation.
BER	Returns the bit error rate (BER). BER is calculated by taking the number of sample errors and dividing it by the total number of samples compared.
BER per channel	Returns the bit error rate (BER) for each channel. BER for an individual channel is calculated by taking the number of bit errors found for that channel and dividing it by the total number of samples compared.
error locations	Returns the bit numbers and the bit locations that were in error for each sample that has an error.
error out	Contains error information. If error in indicates that an error occurred before this Express VI ran, error out contains the same error information. Otherwise, it describes the error status that this Express VI produces.

NI-HSDIO LabVIEW VIs

Table of Contents

NI-HSDIO Express (Acquisition) VI

NI-HSDIO Express (Acquisition) VI (Deprecated)

Block Diagram Inputs

Block Diagram Outputs

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