NIHSDIO_ATTR_TRIGGER_POSITION_DELAY
- Updated2023-02-21
- 1 minute(s) read
Specific Attribute
| Data type |
Access | Applies to | Coercion | High-Level Functions |
|---|---|---|---|---|
| ViReal64 | R/W | N/A | None | None |
Description
Specifies, per channel, the delay after the Sample clock rising edge when the device samples on a trigger. Trigger delay is expressed as a fraction of the clock period (for example, a fraction of 1/Sample clock rate).
 |
Note This attribute is supported only on PFI 1 and PFI 2 on NI 6555/6556 devices. |
Valid values range from –1 to 2 clock cycles in increments of 0.001 cycles.
The default value is 0.