Configure Reference Clock

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Updated2023-02-17
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Configures the Reference clock.

Use this node when you are using the On Board Clock as a Sample clock and you want the Sample clock to be phase-locked to a reference signal. Phase-locking the Sample clock to a Reference clock prevents the Sample clock from losing alignment with the Reference clock. The driver ignores the Reference clock rate input when the Reference clock source is PXI Clock.

Inputs/Outputs

session in

Instrument session obtained from the Initialize Acquisition Sessionnode, the Initialize Generation Sessionnode, or the Initialize External Calibrationnode.

clock source

The specified phase-lock loop (PLL) reference clock source.

None		Configures the device to not phase lock the onboard clock with a Reference clock.
ClkIn		Configures the device to phase lock the onboard clock with the clock signal present at the CLK IN connector.
PXI Clock		Configures the device to phase lock the onboard clock with the clock signal present at the PXI reference clock pin on the PXI backplane. PXI_CLK10 is available for PXI devices, and PXIe_CLK100 is available for PXI Express devices. This clock signal is not supported on PCI devices.
RTSI 7		Configures the device to phase lock the onboard clock with the clock signal present at the RTSI 7 pin on the PCI backplane. This clock signal is not supported on PXI devices.
PXIe DStarA		Configures the device to phase lock the onboard clock with the PXIe_DStarA signal present on the PXI Express backplane. This clock signal is supported only on PXIe-6555/6556 devices.