NIFGEN_ATTR_CLOCK_MODE
- Updated2023-02-21
- 1 minute(s) read
Specific Attribute
| Numeric Value | Data Type | Access | Applies to | Coercion | High-Level Functions |
|---|---|---|---|---|---|
| 1150110 | ViInt32 | R/W | N/A | None | None |
Description
Controls the Sample clock mode for the signal generator.
For signal generators that support it, this property allows switching the Sample clock to a high-resolution clocking mode. When in divide-down sampling mode, the sample rate can only be set to certain frequencies, based on dividing down the update clock. However, in high-resolution mode, the sample rate may be set to any value.
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Note You cannot change this attribute while the device is generating a waveform. If you want to change the device configuration, call the niFgen_AbortGeneration function or wait for the generation to complete. |
Defined Values
| NIFGEN_VAL_DIVIDE_DOWN | Divide down sampling—Sample rates are generated by dividing the source frequency. |
| NIFGEN_VAL_HIGH_RESOLUTION | High resolution sampling—Sample rate is generated by a high–resolution clock source. |
| NIFGEN_VAL_AUTOMATIC | Automatic Selection—NI-FGEN selects between the divide–down and high–resolution clocking modes. |
Default Value: Depends on the device