Pulsed Binary Phase Shift Keying (BPSK) Modem Examples

Pulsed Binary Phase Shift Keying (BPSK) modulation is modulation scheme in which a +1 is mapped to one complex symbol while a -1 is mapped to a different complex symbol.

In Pulsed BPSK modulation demodulation, the input signal is pulsed—instead of being a continuous stream of bits, the input signal is a stream of ON and OFF pulses. A pulsed BPSK symbol constellation may resemble the following figure.
Figure 10. Pulsed BPSK Symbol Constellation

Key Performance Parameters

FPGA IP single cycle timed loop clock rate 120 MHz
Samples per cycle 8
Samples per symbol 2
Maximum symbol rate 120 MHz * (8/2) = 480 MSymbols/s

Modem Details

The modulated signal has a frame structure of a preamble and payload, as shown in the following figure.

Figure 11. Modulated Signal Frame Structure

  • Preamble length is fixed as 32 bits on the demodulator side, due to the fixed structure of the correlator.
  • Configurable bit pattern.
  • Configurable payload length.
  • Fixed two samples/symbol.
  • Pulse width and PRI are defined in symbol count.

Pulsed BPSK FPGA Modulator IP

A brief summary of the functioning of the modulator IP is shown in the following figure.

Figure 12. Modulator IP

  1. A given preamble and payload bitstream are combined to form a frame structure of the bits.
  2. A pulse shaping filter is applied to the bitstream.
  3. Additive White Gaussian Noise (AWGN) is applied to the pulse shaped signal.
  4. Pulse Control is done to create pulsed BPSK modulated data.

Pulsed BPSK FPGA Demodulator IP

A brief summary of the functioning of the demodulator IP is shown in the following figure.

Figure 13. Demodulator IP

  1. The received baseband signal in the form of complex I/Q data goes through the Matched Filter for maximizing the signal-to-noise ratio (SNR).
  2. Depending on the power of the input signal, an Automatic Gain Control (AGC) applies an additional gain to the match filtered signal.
  3. Since this is a pulsed signal, Burst Detection reads the presence of a signal.
  4. The signal is interpolated to assist in the next step of phase offset correction. There are several types of interpolation. In this IP, a parabolic interpolation is performed.
  5. Phase correction is performed on the interpolated signal.
  6. Carrier synchronization and tracking is performed by a PLL.
  7. The resulting signal is ready to be demodulated to bits.

Bit Error Rate (BER) Measurements

The modem IP can perform bit error rate (BER) measurements, based on the demodulated bits, directly on the FPGA. This enables the system to compute BER in real time while the data is being demodulated.

BER measurement is performed under certain assumptions:

  • Bits are part of a Pseudo Random Bit Sequence (PRBS).
  • PRBS resets at the end of the frame.
  • PRBS sequences of degrees: 7, 9, 10, 11, 15, 17, 18, 20, 21, 22, 23, and 25 are supported.
  • PRBS is based on a primitive trinomial of the form 1+xk+xn where tap (k) is selected based on the PRBS degree.

    The values of PRBS degree (n) and the tap (k) of the primitive trinomial are shown in the following table.

Table 21. PRBS Values
PRBS Degree (n) Primitive Trinomial Tap (k) Trinomial Form
7 6 1+x6+x7
9 5 1+x5+x9
10 7 1+x7+x10
11 9 1+x9+x11
15 14 1+x14+x15
17 14 1+x14+x17
18 11 1+x11+x18
20 17 1+x17+x20
21 19 1+x19+x21
22 21 1+x21+x22
23 18 1+x18+x23
25 22 1+x22+x25

Using the Pulsed BPSK Modem Examples and Example Bitfiles

NI Data Link Test Framework provides pulsed BPSK modem examples and example bitfiles in the following locations:

  • Pulsed BPSK modem examples: <LVAddons>\dltf\1\examples\Data Link Test Framework\Modems\Pulsed BPSK
  • Example bitfiles for the Pulsed BPSK modem examples: <LVAddons>\dltf\1\examples\Data Link Test Framework\Modems\Pulsed BPSK\FPGA\FPGA Bitfiles