The CompactRIO reconfigurable embedded chassis, integrated controllers and chassis, Ethernet RIO chassis, and Single-Board RIO (sbRIO) devices have a Scan Clock I/O item. Use the Scan Clock item to monitor when the NI Scan Engine transfers data between the FPGA VI and the RT host VI.

Use the Scan Clock information with user-defined I/O variables to synchronize data transfers with the NI Scan Engine. Synchronizing user-defined I/O variable data transfers with the Scan Engine ensures the coherency of the data sets you transfer between the FPGA VI and the RT host VI.

NI recommends you design the application so that read/write operations occur when the Scan Engine is not transferring data between the FPGA VI and the RT host VI. If you read from or write to user-defined I/O variables while the Scan Engine is transferring data, the Scan Engine cannot guarantee data coherency, and the data transfer gets delayed to the next opportunity.

The following image illustrates how the Scan Engine reacts when you read from or write to user-defined I/O variables during the Scan Engine high time and when a user-defined I/O variable read or write operation misses the falling edge of the Scan Engine.

Figure 2. Scan Engine Reactions to User-Defined I/O Variable Read/Write Operations
Scan Engine Reactions to User-Defined I/O Variable Read/Write Operations

You can also use the Scan Clock information to synchronize the execution of code in the FPGA VI with code in the RT host VI that is synchronized to the Scan Engine.

Use the following Scan Clock I/O item, method, and properties to monitor information from the Scan Engine.

Scan Clock I/O Item

Use the FPGA I/O Node to access the Scan Clock I/O item.

To access the Scan Clock I/O item, drag the Scan Clock I/O item from the Chassis I/O folder in the project to the block diagram of the FPGA VI. You can also place an FPGA I/O Node on the block diagram, click the element section of the FPGA I/O Node, and select Chassis I/O»Scan Clock from the shortcut menu.

  • Scan Clock—returns TRUE when the Scan Clock signal is high and the Scan Engine is not transferring data between the FPGA VI and the RT host VI. Scan Clock returns FALSE when the Scan Clock signal is low and the Scan Engine is transferring data between the FPGA VI and the RT host VI.

    • Scan Clock Method: Wait on Rising Edge

    Use the FPGA I/O Method Node to access the Wait on Rising Edge method for the Scan Clock I/O item.

    The Wait on Rising Edge method pauses the execution of the FPGA I/O Method Node until the next rising edge of the Scan Clock signal or until the Timeout expires.

  • Timeout—specifies in FPGA clock ticks how long the Wait on Rising Edge method waits for the next rising edge. A value of 0 causes the method to time out immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out.
  • Timed Out—returns TRUE if a timeout occurred.
  • Missed Falling Edge—returns TRUE if the method detects one or more falling edges of the Scan Clock signal after the last execution of the method and before the current execution. The first time the method executes, Missed Falling Edge returns FALSE. Use the Missed Falling Edge and Missed Rising Edge outputs to monitor if the FPGA VI is synchronized with the Scan Engine.
  • Missed Rising Edge—returns TRUE if the method detects one or more rising edges of the Scan Clock signal after the last execution of the method and before the current execution. The first time the method executes, Missed Rising Edge returns FALSE. Use the Missed Falling Edge and Missed Rising Edge outputs to monitor if the FPGA VI is synchronized with the Scan Engine.
  • High Time—displays the number of FPGA clock ticks that the Scan Clock signal was high during the last period of the signal. During the first period of the Scan Clock signal, High Time returns 0. The High Time output of the Wait on Rising Edge method performs the same as the High Time property accessible from the FPGA I/O Property Node.

    • Scan Clock Properties

    Use the FPGA I/O Property Node to access the following properties for the Scan Clock I/O item.

  • Enabled—returns TRUE when the Scan Engine is enabled. Enabled returns FALSE if the Scan Engine has not started, is reconfiguring, or has stopped
  • High Time—displays the number of FPGA clock ticks that the Scan Clock signal was high during the last period of the signal. During the first period of the Scan Clock signal, High Time returns 0. The High Time property performs the same as the High Time output of the Wait on Rising Edge method.

    • Example VIs

    Refer to the User-Defined IOV Synchronized VI in the labview\examples\CompactRIO\NI Scan Engine\Advanced\Scan Engine Synchronization\Scan Engine Synchronization.lvproj for an example of using the Scan Clock I/O item and the Wait for Rising Edge method with user-defined I/O variables.

    Refer to the User-Defined IOV Advanced Sync VI in the labview\examples\CompactRIO\NI Scan Engine\Advanced\Scan Engine Synchronization - Advanced\Scan Engine Synchronization - Advanced.lvproj for an example of using the Scan Clock I/O item and the Wait for Rising Edge method, including the High Time output, with user-defined I/O variables.