Programmatically Resetting the System on a CompactRIO Chassis or sbRIO Device

Use a digital output line to programmatically reset the system.
  1. Configure a project for the system.
  2. Make sure the System Reset I/O item is added to the system.
  3. Right-click the FPGA target in the Project Explorer window and select New»VI from the shortcut menu to add a new FPGA VI to the system.
  4. Place an FPGA I/O Node on the block diagram of the FPGA VI.
  5. Click the element section of the FPGA I/O Node and select Chassis I/O (or Onboard I/O)»System Reset.
  6. Right-click the System Reset input of the FPGA I/O Node and select Create»Control. When System Reset is TRUE, the system resets.
    The system FPGA deasserts the System Reset line during the system reset. You do not need to wire a FALSE Boolean value to the System Reset input or ensure that the System Reset input is TRUE for a minimum amount of time.
    Caution   If the FPGA VI uses the System Reset output and you configure the system to load the FPGA VI when there is a software or hardware reset, make sure that the system is not set up in a way in which the system continually resets before you run the FPGA VI. If the system is in a state in which it continually resets, contact NI support.
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