NI 6585/6585B CLIP

The NI 6585/6585B ships with socketed CLIP that adds module I/O to the LabVIEW project. The NI-developed NI 6585/6585B CLIP are as follows:
  • NI 6585 Basic Channel—Provides read/write access to all low-voltage differential signal (LVDS) channels using a simple channel-based interface. Each I/O line has a write enable signal. This CLIP provides a clock signal for export on each connector. The clock inputs from the NI 6585 are passed to LabVIEW FPGA for use in the FPGA VI. This CLIP also allows for individual clock output inversion.
  • NI 6585 Basic Connector CLIP—Provides read/write access to all low-voltage differential signal (LVDS) lines on each connector, where the lines are grouped per connector. The individual data lines for each connector are accessed using a U16 data type in LabVIEW FPGA. Each I/O line has a write enable signal. This CLIP also allows for individual clock output inversion.
  • NI 6585 DDR Connector CLIP—Provides read/write access to all low-voltage differential signal (LVDS) lines on each connector, where the lines are grouped per connector. The individual datalines for each connector are accessed using a U16 data type in LabVIEW FPGA. Data from each edge of the clock is presented as “rising” and “falling.” Each I/O line has a write enable signal. This CLIP also allows for individual clock output inversion.
    • Note Refer to the FlexRIO Help for information about FlexRIO CLIP, configuring the NI 6585/6585B with a socketed CLIP, and a list of available socketed CLIP and provided signals.