The /table command is used to specify an output truth table which specifies output variable values as a function of input variables, and, in the case of sequential logic, of state variables. This command is fundamental to the Digital Chip device and must be present in all cases. The /table command has a single parameter that describes the number of lines, or rows, in the truth table that follows in the subsequent lines. The columns in the table represent the set of all input and output node variables in the order that they were defined. All input combinations possibilities must be exhausted by the truth table. However, using the symbol 'X' to a denote "Don't Care" conditions can dramatically reduce the number of rows in the table. Below is an example of an AND gate.

U1  [in1 in2] [out] myAND
.model myAND d_chip(behaviour= "
+;Simple And gate
+/inputs  A B
+/outputs Y
+/table 2
+;A B Y
+H H H
+X X L
+")

During simulation, scanning from top to bottom, the simulator evaluates the first 'true' condition in the truth table As such, when specifying "Dont Care" conditions it is important to specify them in the right order.