/clock

Description of sequential logic is made possible using the /clock command. The description of the logic resembles a state transition table used in the design of finite state machines (FSMs). Both synchrounous and asynchrounous logic is supported. The /clock command and its parameters are as follows:

/CLOCK  clk_name  edge  NumOfFlags  NumOfSync  NumOfAsync

The /clock command must be followed by a synchronous state transition table. This table is used to assign values to the state flags and is evaluated when the clk_name variable makes a transition as defined by the edge parameter. The first set of columns correspond to the inputs variables. The next set of columns correspond to the current state flags - the state just before the edge. The current state flags, together with the input variables, are the inputs to the truth table. The last set of columns correspond to the next state flags - the state just after the edge. The next state flags are the outputs of the truth table. The number of columns in each current state and next state fields must equal NumOfFlags. Note that values of the flags are overwritten with every evaluation of the synchronous truth table.

The asyncronous state transition table, which directly follows the synchronous transition table, is identical in every way except one: it is evaluated whenever any of the other inputs (that is, non-clock inputs) make a transition (LOW->HIGH or HIGH->LOW).

Note that neither the synchronous truth table nor the asyncronous truth table actually write values into any of the output variables; the output truth table (/table command) must be used for that. In the context of the /clock command, since the output is a function of both the current state and input signal, the output truth table has extra column(s) for the current state flags.

The description of sequential logic using the /clock command is best illustrated by an example. Consider the following description of a D-type flip-flop.

aU1  [D Set Clear Clk] [Out notOut] logic
.model logic d_chip(behaviour= "
+/inputs D SD CD CP
+/outputs O  ~O
+;clock input_number edge{+|-} number_of_flags sync_entries
async_entries
+/clock CP + 1 2 3
+;The synchronous table
+; D  SD  CD  CP CurrentFlagState  NextFlagState
+H X X X X H
+L X X X X L
+;The asynchronous table
+; D  SD  CD  CP CurrentFlagState  NextFlagState
+ X H X X X H
+ X X H X X L
+ X X X X X F0
+;The output table
+/table 1
+; D  SD  CD  CP Flag   O1  ~O1
+  X   X   X     X     X     F0   ~F0
+")

Since the Flip-Flop only has two states, a single flag, or bit, is required to represent them. We represent the state when output is LOW using the LOW value and the state when the output is HIGH using a HIGH value. When the signal "CP" makes a LOW->HIGH transition, the synchronous truth table is evaluated, updating the next state flags (i.e the contents of F0). The output truth table is evaluated afterwards, updating the output variables. Note that in this example, the values that were chosen to represent the states correspond directly to the output values. As such, only a single entry, which copies the value of state flags to the outputs variables regardless of the input, is required in the output table.

When any of the non-clocked signals make a transition, the asynchronous table and the output table are evaluated in a similar fashion. Note that when the Set or Clear signals are not individually HIGH, the state is maintained by the copying of the present state flag to the next state flag.