Set Custom Bitfile VI

Owning Palette: Device Management VIs

Requires: myRIO Toolkit or roboRIO Toolkit

Sets a custom FPGA reference.

Details  Examples

	Custom FPGA Reference In specifies the input custom FPGA reference.
	error in describes error conditions that occur before this node runs. This input provides standard error in functionality.
	Custom FPGA Reference Out returns the custom FPGA reference.
	error out contains error information. This output provides standard error out functionality.

Set Custom Bitfile Details

You must set a custom FPGA reference before using a custom FPGA bitfile with the myRIO VIs or the roboRIO VIs. Use the Open FPGA VI Reference function to open a reference to the custom FPGA bitfile. Use the Close FPGA VI Reference function to close the reference at the end of an application.

Related Information

Open FPGA VI Reference Function

Close FPGA VI Reference Function

Examples

Refer to the following VIs for examples of using the Set Custom Bitfile VI:

• labview\examples\myRIO\Customized FPGA\Customized FPGA Signal Generator.lvproj
• labview\examples\roboRIO\Customized FPGA\Customized FPGA Signal Generator.lvproj