Parallel operations on the FPGA typically increase execution rate and reduce jitter when compared to processor-based targets. Each parallel operation executes on its own dedicated section of FPGA hardware to achieve truly simultaneous execution. As a result, the total execution time of parallel FPGA operations equals the execution time of the slowest operation, whereas the total execution time of the same operations on a single processor equals the sum of all the execution times.

To create parallel operations, use multiple independent While Loops on a single block diagram. For example, you can implement multiple data acquisition engines, each with an independent sampling rate, as shown in the following block diagram.

You can use independent sampling rates to efficiently acquire data in systems that contain both high frequency and low frequency signals. Configure one data acquisition engine with a high sampling rate to measure a high frequency signal. Configure the other data acquisition engine with a lower sampling rate to measure a low frequency signal.

If you use shared resources among parallel operations, you risk disabling parallel execution, as each operation must wait for the shared resource to become available before executing. Possible shared resources include digital I/O resources, analog I/O resources, memory items, register items, the interrupt line, local and global variables, and non-reentrant subVIs.

Tip Each parallel operation uses a certain amount of space on the FPGA. If you begin to run out of space on the FPGA and have identical parallel operations, you can save space by creating a subVI for the operation and making it non-reentrant. However, you sacrifice parallel execution by creating a non-reentrant subVI for the operation.

Using wires to transfer data between loops introduces a dataflow dependency that prevents the loops from running in parallel.

  • Memory items
  • Register items
  • Local or global variables
  • FIFOs