When you use third-party simulation, understanding the simulation export VHDL framework can help you successfully debug the FPGA VI.

The test bench framework, tb_NiFpgaSimulationModel, contains a hierarchy of models necessary for simulation, as shown in the following illustration.

The following list describes the components of the simulation test bench in more detail.

tb_NiFpgaSimulationModel—The default name of the overarching test bench framework. The name always begins with tb_and ends with the name you specify in the Top-level simulation model name text box on the Information page of the Simulation Export Properties dialog box.

  • Main stimulus process—Add code here to set controls, read indicators, and perform other stimulus for the FPGA VI. Enter the code you want between the NiFPGA_Run and NiFpga_Close lines.
  • NiFpgaSimulationModel—The simulation model.
    • NiFpgaSimInterface—The bus interface, or the VHDL that LabVIEW provides to communicate with the target-specific code. The name always begins with NiFpgaSim and includes interface. Other parts of this name depend on the target.
    • Toplevel Framework—Target-specific code. The exact name of this model grouping varies by target.
      • TheWindow—The code that you want to interact with. TheWindow groups CLIP code and FPGA VI code.
        • Clip—The CLIP simulation code for the CLIP instances you specify in the LabVIEW project. You specify the simulation behavior for the CLIP on the Name and Source page of the Configure Component-Level IP wizard. Any code under this model grouping is user-defined.
        • TheVI—The code that LabVIEW generates for the FPGA VI. LabVIEW derives the name of TheVI from the name of the top-level VI you specify on the Source Files page of the Simulation Export Properties dialog box.
          • Controls and indicators—Code for the controls and indicators in the FPGA VI. This part of the model also contains code to handle resetting the FPGA VI.
          • VI logic—This part of the model contains code to run the VI logic from the block diagram of the FPGA VI. The code hierarchy in this part of the model reflects the hierarchy of the block diagram. For example, entities in the model such as single-cycle Timed Loops, Flat Sequence structures, and Case structures contain VHDL code to represent the nodes found in these structures on the block diagram.
        • (Optional) I/O Stimulus/Response—This part of the model contains code that you add to simulate FPGA target I/O.

Details for VI Logic Found under TheVI

Structures with multiple subdiagrams, such as Case structures and Flat Sequence structures, have a separate VHDL entity for each case or frame. These VHDL entities have names ending with _diag to indicate that they represent a subdiagram.

Reentrant subVIs appear in the VHDL code in the same manner as structures appear. Reentrant subVIs have multiple instances in the VHDL code hierarchy. These instances correspond to calls to the subVIs from the block diagram.

Non-reentrant subVIs include special VHDL logic to manage the data flow to and from reentrant subVIs.

The VHDL code also contains entities representing LabVIEW VIs and functions. Most of these elements are encrypted, but you can see incoming and outgoing values on their port maps.