Throughput Conventions in FPGA-Based Systems

Learn how to interpret throughput metrics across FPGA‑based systems by using consistent units, conversions, and multi‑channel scaling rules.

Throughput in FPGA‑based systems can appear in different unit conventions depending on the data‑path design. The following sections describe how to interpret these units consistently and how to relate them to multi‑channel behavior and clock‑rate constraints.

Unified Throughput Relationships

Use these relationships to translate between system throughput and channel throughput across throughput conventions:
  • System Throughput = Channel Throughput ÷ Number of Channels
  • Channel Throughput = System Throughput × Number of Channels
After verifying timing feasibility, select a throughput unit that matches the processing model.
Note For system and channel throughput used in a wiring procedure, see Wiring Single‑Input Nodes Using Handshaking.

Throughput Unit Conventions

FPGA products use two primary conventions to express throughput. Each convention aligns with the operating model of the data path.
  • cycles/sample—Common in industrial and embedded systems such as cRIO‑class devices, where processing of a single data sample often requires multiple FPGA clock cycles. Throughput expressed as cycles/sample indicates the number of cycles needed to accept or produce one sample.
  • samples/cycle—Used in streaming pipelines such as RF systems and communication systems, where data paths typically operate at or near one sample per clock cycle. Throughput expressed as samples/cycle indicates how many samples the system moves per clock cycle.

    • Unit Conversions

    To convert between conventions, invert the following value:
    • System Throughput (samples/cycle) = 1 ÷ System Throughput (cycles/sample)
    To compute throughput from the clock rate or the sample rate, use one of the following equations:
    • System Throughput (cycles/sample) = Clock Rate (cycles/second) ÷ Sample Rate (samples/second)
    • System Throughput (samples/cycle) = Sample Rate (samples/second) ÷ Clock Rate (cycles/second)

    Interpreting Throughput as a Spacing Constraint

    In single‑cycle Timed Loop handshaking, throughput is a key concept. Throughput, denoted as Tf, represents the minimum number of clock cycles required. This value is the time that must elapse before a node can accept a new valid input after starting computation.

    This definition naturally expresses in cycles/sample, because Tf represents minimum spacing between accepted samples in clock cycles. A smaller Tf supports more frequent acceptance of new samples.

    Note For throughput limits in single‑cycle Timed Loop scheduling, see Scheduling Timing Using Handshaking Signals.

    Multi-Channel Designs: Interpretation and Interleaving

    Some multi‑channel nodes interleave values across channels in sequence. The data points distribute across channels in a sequential pattern, starting from channel 0.
    • Channel 0 receives the first valid data point.
    • Channel 1 receives the second valid data point.
    • This pattern continues for subsequent channels.

    Interleaving changes interpretation of per‑channel rates because scheduling distributes a single stream of valid samples across channels. Apply the system and the channel throughput relationships to interpret per‑channel rates in interleaved designs.

    Note For details about interleaving behavior in multi‑channel handshaking, see Scheduling Timing Using Handshaking Signals.

    Timing Report Clock Metrics and Throughput Metrics

    Compilation reports use Requested (MHz) to describe the timing feasibility of the compiled logic. These metrics do not describe data throughput.
    • Requested (MHz) indicates the clock rate at which an FPGA VI or an FPGA VI component must operate.
    • Maximum (MHz) indicates the theoretical maximum compilation rate for an FPGA VI or an FPGA VI component.

    If the Requested (MHz) is greater than the Maximum (MHz), the design does not meet timing constraints. As a result, compilation can fail in the final timing stage.

    Use these MHz values to evaluate whether the design meets timing for a selected clock.

    • Select cycles/sample to evaluate how frequently a design can accept samples.

    • Select samples/cycle to evaluate how frequently a design can process samples.

    • Select one of these throughput unit to evaluate how frequently a design can produce samples.

    Note For definitions and usage of Requested (MHz) and Maximum (MHz) in reports, see Reports Available from the Compilation Status Window.

    Guidance for Use

    Complete the following steps when planning or reviewing throughput:
    1. Select a primary throughput convention that matches the operating model of the data path.
      • For multi‑cycle scheduling, select cycles/sample.
      • For streaming pipelines, select samples/cycle.
    2. Calculate system throughput from clock rate and sample rate when a design starts with MHz and MS/s requirements.
    3. Scale between system throughput and channel throughput using the channel count.
    4. Compare system throughput against Tf values of nodes in a processing chain to identify acceptance‑rate limits.
    5. Validate timing feasibility using Requested (MHz) and Maximum (MHz) in compilation reports. Timing feasibility constrains usable clock rate.

    Examples

    Use these examples to relate throughput units, clock rate calculations, and channel-scaling rules.

    • Converting cycles/sample and samples/cycle:
      A clock rate of 40 MHz and a sample rate of 2 MS/s yields 20 cycles per sample. This value corresponds to 0.05 samples per cycle.
      • 40,000,000 ÷ 2,000,000 = 20 cycles/sample
      • 2,000,000 ÷ 40,000,000 = 0.05 samples/cycle
    • Scaling throughput across channels (cycles/sample):
      A system throughput of 200 cycles/sample across 4 channels yields 800 cycles/sample for channel throughput.
      • Channel Throughput = 200 × 4 = 800 cycles/sample
    • Scaling throughput across channels (samples/cycle)
      • A system throughput of 0.5 samples/cycle across 8 channels yields 0.0625 samples/cycle per channel.
        • Channel Throughput = 0.5 ÷ 8 = 0.0625 samples/cycle per channel