Preparing IP for Use with the IP Integration Node

The following tables describe recommendations and requirements for using IP with the IP Integration Node.

Recommendations for All IP

The following recommendations apply to all IP you use with the IP Integration Node.

Recommendation Details

Use VHDL. The IP Integration Node is designed to work best with VHDL. Using Verilog limits the available simulation options. To integrate Verilog code, first compile the code into a netlist file. You then can use this file with the IP Integration Node.

Validate the IP outside of LabVIEW. The IP Integration Node is not a debugging or testing environment. Before integrating the IP into the IP Integration Node, NI recommends validating IP by synthesizing it using the Xilinx compilation tools first. You also can create a test bench in a third-party simulation tool to ensure the IP is robust.

Synchronize IP output ports to the rising edge of the single-cycle Timed Loop clock. Synchronizing output ports to the rising edge of the single-cycle Timed Loop clock ensures that simulating the FPGA VI produces the same results as executing the VI on an FPGA target.

Requirements for All IP

The following requirements apply to all IP you use with the IP Integration Node.

Note Ports below the top level can be of any data type.

Recommendations for IP that Contains Sequential Logic

Sequential logic is logic that uses one or more FPGA logic elements, such as flip-flops, to store its state from one clock cycle to the next. Examine the IP to determine whether it contains any sequential logic. If it does, the following recommendations apply to the IP. If the IP does not contain any sequential logic, the IP is combinatorial.

Note If the IP does not include an enable signal and the FPGA VI resets, LabVIEW might discard the initial values of the IP before the single-cycle Timed Loop can start executing. The lack of an enable signal means nothing prevents the IP from clocking in garbage data while other block diagram functions initialize.

Recommendation for IP that Contains Only Combinatorial Logic

Combinatorial logic is logic that does not store its state, that is, logic that is not sequential. If the IP does not contain any sequential logic, the IP is combinatorial. Complete the following steps if the IP contains only combinatorial logic:

  1. Double-click the IP Integration Node and navigate to the Clock and Enable Signals page.
    Note If the node is configured already, you can right-click the node and select Configure»Clock and Enable Signals from the shortcut menu.
  2. In the Clock signal name pull-down list, select No clock signal.
  3. Click the OK button to save changes and return to the block diagram.

The IP Integration Node now treats the IP as combinatorial.