The LabVIEW FPGA Module provides an option to export an FPGA VI as a Vivado Design Suite project. This option allows you to design the exported project and compile it into a bitfile in the Vivado Design Suite. You can then run the bitfile on an FPGA target, such as a Kintex-7 FlexRIO target or a High-Speed Serial Instrument, in the FPGA Module. This option takes advantage of the design features provided by the Vivado Design Suite while making full use of NI FPGA hardware resources. The following sections outline the exporting process.

Note   
  • Not all targets support Vivado Design Suite project export. Refer to the specific FPGA target hardware documentation for information about exporting options available for the target.
  • You must install the necessary Xilinx compilation tool for Vivado on the local computer to export an FPGA VI as a Vivado Design Suite project or open the exported project. Visit ni.com/info and enter the Info Code XilinxCompileTools for more information about NI hardware and LabVIEW versions supported by each version of Xilinx compilation tool for Vivado. Refer to the Xilinx Compilation Tools Readme for instructions on installing the Xilinx compilation tool for Vivado.

Exporting an FPGA VI

You must export an FPGA VI as a Vivado Design Suite project before you can design the project and compile it into a bitfile that can be deployed to an FPGA target. To export an FPGA VI, you first must create a build specification.

Note   To allow design of the exported project in the Vivado Design Suite, you must integrate third-party IP into the FPGA VI and name the design files so that the filenames start with UserRTL_. For example, you can name your VHDL file as UserRTL_FpgaTop.vhd. All the design files generated for the export are encrypted except those with filenames that start with UserRTL_.

Complete the following steps to export an FPGA VI through the Project Explorer window:

  1. Right-click Build Specifications in the Project Explorer window and select New»Project Export for Vivado from the shortcut menu to display the Project Export for Vivado Design Suite Properties dialog box. You also can right-click an existing build specification for the Vivado Design Suite project export and select Properties from the shortcut menu to display this dialog box.
  2. Specify the build specification name and other descriptive information on the Information page.
  3. Display the Source Files page to specify the top-level VI. FPGA VIs can have only one top-level VI.
  4. Click OK to close the dialog box or click Build to begin exporting the FPGA VI. After you click Build, LabVIEW creates the files necessary for the export and places the files in the export directory that you specified in step 2.
    Note   If you make further changes to the FPGA VI after exporting it as a Vivado Design Suite project, you can integrate your changes to the existing project by right-clicking the Vivado Design Suite project under Build Specifications and selecting Build or Rebuild.

Designing and Compiling an Exported Project

After you export the FPGA VI as a Vivado Design Suite project, you can continue to design and compile the exported project in the Vivado Design Suite. You can open the project in the following ways:

  • In the Project Explorer window, right-click the project under Build Specifications and select Launch Vivado Design Suite.
  • In the Project Explorer window, right-click the project under Build Specifications and select Explore to open the export directory. Open LaunchVivadoDesignSuite.bat in the export directory.
  • Navigate to the export directory and open LaunchVivadoDesignSuite.bat.
Note   When you export the FPGA VI as a Vivado Design Suite project, FPGA automatically configures the -flatten_hierarchy and -keep_equivalent_registers settings under Project Settings»Synthesis, and the tcl.post setting under Project Settings»Implementation»Write Bitstream (write_bitstream) in the Vivado Design Suite. The tcl.post setting ensures that the bitfile generated from the exported project can be deployed to an NI FPGA target. NI recommends that you keep these settings when designing your project in the Vivado Design Suite.

Refer to the Vivado Design Suite documentation for more details about designing the exported project and compiling it into a bitfile.

Running a Bitfile Generated from the Exported Project

After you generate a bitfile for your exported project in the Vivado Design Suite, you must create a host VI in the FPGA Module to programmatically download or run the bitfile using programmatic FPGA interface communication.

Where to Go from Here

Refer to the device-specific examples to learn more about exporting an FPGA VI as a Vivado Design Suite project. To access the device-specific examples, select Help»Find Examples from LabVIEW to launch the NI Example Finder. Click the Browse tab to locate device-specific examples or click the Search tab to search all installed examples by keyword.