You can create an n-tap FIR filter by using n DSP48E functions. Each function processes one coefficient, or tap, of the FIR filter, where h[0..n–1] represents the n coefficients of the FIR filter. Complete the following steps to create a 3-tap FIR filter.

  1. Create a new, blank VI on a supported FPGA target.
  2. Add a DSP48E function to the block diagram.
  3. Double-click this function and configure it in the following ways:
    1. Function page:

    2. Terminals page:

    3. Click the OK button to save changes and return to the block diagram.
  4. Add another DSP48E function to the block diagram. Configure this function in the following ways:
    1. Function page:

    2. Terminals page:

    3. Click the OK button to save changes and return to the block diagram.
  5. Press the <Ctrl> key and drag this node to create a copy on the block diagram. Repeat this step until there are a total of n DSP48E functions on the block diagram. In this example for a three-tap filter, there are three DSP48E functions on the block diagram.
  6. Double-click the nth function, click the Terminals tab, and remove the checkmark from the pcout checkbox.
  7. Click the OK button to save changes and return to the block diagram.

  8. Wire the functions and terminals together.
    1. Wire the data to filter to the a input of each DSP48E function. Depending on the source for this input, you might need to adjust the integer word length of the a input.
    2. Wire each individual filter coefficient to the b input of each successive DSP48E function. You might need to scale values you wire to these terminals.
    3. Wire each pcout output terminal to the pcin input terminal of the next DSP48E function.
    4. The p output terminal of the last DSP48E function returns the filtered data. Either create an indicator for this function or wire it to another function.
  9. The block diagram now resembles the following figure:

  10. Save the VI to a convenient location as DSP48E FIR Filter.vi.

In the previous figure, the a input of each function processes the data you want to filter. The b input processes the filter coefficients h[0] through h[n–1] for a total of n coefficients, one for each DSP48E function.

Tip If n is large, the following recommendations apply:
  • Large arrays consume significant space on an FPGA. Therefore, NI recommends using other methods to store the coefficients, such as memory items. You also can use the Discrete Delay function to store multiple coefficients for a series of clock cycles.
  • The block diagram will have a lot of DSP48E icons on the block diagram. You can shrink these icons to reduce the amount of space each icon uses.

You now can export this VI for simulation. To run this VI on an FPGA target, you must enclose the code in a single-cycle Timed Loop.