For some FPGA targets, you can configure the FPGA base clock and set it as the top-level clock in the project to control execution rates. You also can use a derived clock to circumvent base clock configuration restrictions. Different FPGA targets support different FPGA-derived clocks. For information on allowed base clock configurations for different FPGA targets, refer to the specific FPGA target hardware documentation.

Complete the following steps to create an FPGA-derived clock to control the execution rate of items on the block diagram.

Note   If you use a base clock or derived clock for the timing source of a single-cycle Timed Loop, the code inside the single-cycle Timed Loop executes at the base clock or derived clock rate. If you configure an FPGA base clock or create a derived clock and set it as the top-level clock, you control the execution rate of the code outside of the single-cycle Timed Loop.
  1. Create a new project or open an existing project.
  2. Add an FPGA target to the project.
  3. Create an FPGA-derived clock to run at the execution rate you want.
  4. Set the FPGA-derived clock as the top level clock.
Note   Not all FPGA VIs have the same maximum clock rate. The complexity of the FPGA VI can affect the maximum execution rate on the FPGA target. If you select aclock rate that is too high for the FPGA VI, the Timing Violation Analysis window returns information about the functions and components that fail to meet the timing objectives.