CLIP Tutorial, Part 4: Passing Data between CLIP and VIs

You pass data between component-level IP (CLIP) and VIs using an FPGA I/O Node in an FPGA VI.

Complete the following steps to use an FPGA I/O Node to access CLIP I/O.

1. In Demo CLIP.lvproj, right-click the FPGA target and select New»VI from the shortcut menu to create a new FPGA VI.
2. Add a Flat Sequence structure to the FPGA VI.
3. Drag the PortA I/O item from the project to inside the Flat Sequence structure.
4. Right-click the Adder CLIP/Port A input, select Create»Constant from the shortcut menu, enter a value of 5 for the constant, and label the constant Offset.
5. Right-click the Flat Sequence structure and select Add Frame After from the shortcut menu.
6. Drag the PortB I/O item from the project to inside empty frame of the Flat Sequence structure.
7. Right-click the Adder CLIP/Port B input on the FPGA I/O Node, select Create»Control from the shortcut menu, and label the control Position.
8. Expand the FPGA I/O Node to add AdderOut.
9. Right-click the Adder CLIP/AdderOut output, select Create»Indicator from the shortcut menu, and label the indicator Position + Offset.
10. Include the FPGA I/O Node within a While loop, as shown in the following block diagram:

The block diagram writes a constant, which is an offset value, to the Port A input. In the While Loop, the FPGA I/O Node adds the offset to a position to create a new position.