Each FPGA target provides at least one clock to control the internal operations of the FPGA. FPGA target clocks determine the execution rate of the individual VIs and functions on the FPGA VI block diagram. You can compile FPGA VIs with faster clock rates for higher performance. However, not all FPGA VIs can compile properly with faster clock rates. If you select a clock rate that is too fast for the FPGA VI, the Compilation Status window tells you the compilation failed because of a timing violation. You must fix the timing violation and try to compile again.

You can change the top-level FPGA target clock rate for an FPGA target by right-clicking the FPGA target in the Project Explorer window and selecting Properties from the shortcut menu. On the Top-Level Clock page of the FPGA Target Properties dialog box, you can set the top-level clock. You also can change the clock rate for a single-cycle Timed Loop within an FPGA VI by double-clicking the Input Node and selecting a clock rate in the Configure Timed Loop dialog box. You can select the FPGA target top-level clock or a clock you derive from the FPGA target base clock.

If you change the top-level FPGA target clock rate or the clock rate of a single-cycle Timed Loop in the FPGA VI, you must recompile the FPGA VI.