You cannot use probes and other traditional LabVIEW debugging techniques in FPGA VIs. If you have unused I/O resources on the FPGA target, you can add additional I/O terminals to the FPGA VI block diagram for debugging. You can monitor the additional I/O terminals using an external device, such as an oscilloscope, logic analyzer, and so on. Examples of using additional I/O terminals to monitor FPGA VIs include the following:

  • Output the internal state of Boolean logic on a digital output terminal.
  • Write a pattern to multiple digital output terminals to indicate when specific portions of the data flow execute.
  • Pulse a digital output terminal to indicate when a trigger has been detected.
  • Toggle a digital output terminal at each iteration of a loop to monitor the performance of the loop.

For example, complete the following steps to monitor the performance of a While Loop in an existing FPGA VI by toggling a digital output terminal at each iteration of the While Loop.

  1. Create a new VI or open an existing VI under an FPGA target that also contains FPGA I/O items in the Project Explorer window.
  2. Create a new FPGA I/O item or select an unused FPGA I/O item that is under the FPGA target you are using in the Project Explorer window.
  3. Right-click the While Loop and select Add Shift Register from the shortcut menu.
  4. Add an FPGA I/O Node inside the While Loop.
  5. Click the I/O Name section of the FPGA I/O Node and select the FPGA I/O item you previously added to the project.
  6. If the FPGA I/O item is a digital input, right-click the FPGA I/O Node and select Change to Write.
  7. Wire the left shift register to the input of the FPGA I/O Node.
  8. Add a Not function to the While Loop.
  9. Wire the x input of the Not function to the wire connecting the shift register and the FPGA I/O Node. Wire the .not. x? output of the Not function to the right shift register.
  10. Select File»Save All in the Project Explorer window to save changes to the FPGA VI and the LEP file.
  11. Recompile and run the FPGA VI on the FPGA target.
  12. Monitor the state of the digital output terminal you selected using an oscilloscope or similar instrument.