CD Verify if Delayed VI

Owning Palette: Model Information VIs

Requires: Control Design and Simulation Module

Checks if the input model has any nonzero input delays, output delays, or transport delays. Wire data to the State-Space Model input to determine the polymorphic instance to use or manually select the instance.

CD Verify if Delayed (State-Space)

	State-Space Model contains a mathematical representation of and information about a system that this VI checks for the presence of any time delays.
	error in describes error conditions that occur before this node runs. This input provides standard error in functionality.
	If Transport Delay? is FALSE, the system transport delay is zero.
	If Delay? is TRUE, a time delay exists in the model.
	If Input Delay? is FALSE, the system input delay is zero.
	If Output Delay? is FALSE, the system output delay is zero.
	error out contains error information. This output provides standard error out functionality.

CD Verify if Delayed (Transfer Function)

	Transfer Function Model contains a mathematical representation of and information about the system that this VI checks for the presence of any time delays.
	error in describes error conditions that occur before this node runs. This input provides standard error in functionality.
	If Transport Delay? is FALSE, the system transport delay is zero.
	If Delay? is TRUE, a time delay exists in the model.
	If Input Delay? is FALSE, the system input delay is zero.
	If Output Delay? is FALSE, the system output delay is zero.
	error out contains error information. This output provides standard error out functionality.

CD Verify if Delayed (Zero-Pole-Gain)

	Zero-Pole-Gain Model contains a mathematical representation of and information about a system that this VI checks for the presence of any time delays.
	error in describes error conditions that occur before this node runs. This input provides standard error in functionality.
	If Transport Delay? is FALSE, the system transport delay is zero.
	If Delay? is TRUE, a time delay exists in the model.
	If Input Delay? is FALSE, the system input delay is zero.
	If Output Delay? is FALSE, the system output delay is zero.
	error out contains error information. This output provides standard error out functionality.