Returns the value wired to the t input or f input, depending on the value of s. If s is TRUE, this function returns the value wired to t. If s is FALSE, this function returns the value wired to f.

The connector pane displays the default data types for this polymorphic function.


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Inputs/Outputs

  • cdbl.png t —

    t is the value that this function returns if s passes a TRUE value.

    t and f must be of the same type, but they can have different numeric representations.
  • cbool.png s —

    s determines whether the function returns the value of t or f in s? t:f.

    If you wire an error cluster to s and an error occurs, the error cluster passes a TRUE value to the function. Otherwise, the error cluster passes a FALSE value to the function.
  • cdbl.png f —

    f is the value that this function returns if s passes a FALSE value.

    t and f must be of the same type, but they can have different numeric representations.
  • idbl.png s? t:f —

    s? t:f is the value wired to t if s is TRUE. s? t:f is the value wired to f if s is FALSE.

    • FPGA Module Details

    The following details apply when you use this object in an FPGA VI.

    Note The following details are subject to change with each version of the LabVIEW FPGA Module.
    Single-Cycle Timed Loop Supported.
    Usage If you use this function with the single-precision floating-point data type, refer to the Using the Single-Precision Floating-Point Data Type and Deciding Which Data Type to Use in FPGA Designs topics for resource use, latency, and single-cycle Timed Loop support implications.
    Timing

    Inside single-cycle Timed Loop--When you use Comparison functions inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the width of the data types you compare.

    Outside single-cycle Timed Loop--When you use Comparison functions outside a single-cycle Timed Loop, each Comparison function takes one clock cycle.

    If you use the Comparison functions with the fixed-point data type, the overflow and rounding modes might impact timing.

    Resources The Comparison functions use FPGA resources in proportion to the width of the data types you compare.