Computes the integer quotient and the remainder of the inputs. This function rounds floor(x/y) to the nearest integer towards -inf.

The connector pane displays the default data types for this polymorphic function.


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Inputs/Outputs

  • cdbl.png x —

    x can be a scalar number, array or cluster of numbers, array of clusters of numbers, and so on.

  • cdbl.png y —

    y can be a scalar number, array or cluster of numbers, array of clusters of numbers, and so on.

  • idbl.png x-y*floor(x/y) —

    x-y*floor(x/y) is the remainder.

    This corresponds to the modulo function of text-based programming languages. When y is 1, the remainder is the fractional part of x.

  • idbl.png floor(x/y) —

    floor(x/y) is the integer quotient. If either input is a floating-point number, the quotient is a floating-point number with an integer value.

    When y is 1, the quotient is the integer part of x.

    • If the integer input value of y is zero, the quotient is zero and remainder is dividend x. For floating-point inputs, if y is zero, the quotient is infinity and the remainder defaults to NaN.

    Note Not all real numbers can be represented in the ANSI/IEEE standard floating-point numbers. Because of this, LabVIEW may encounter rounding errors and yield unexpected results if you use floating-point numbers with this function. For exact calculations and comparisons, convert floating-point numbers to integers.

    FPGA Module Details

    The following details apply when you use this object in an FPGA VI.

    Note The following details are subject to change with each version of the LabVIEW FPGA Module.
    Single-Cycle Timed Loop Not supported.
    Usage

    Division is a relatively expensive operation on the FPGA in terms of both resource usage and time. Use the Scale By Power of 2 function with n wired as a negative constant to increase efficiency when dividing by a power of two.

    This function does not support the single-precision floating-point data type.
    Timing This function requires clock cycles and registers in proportion to the number of bits in x or y, whichever data type is larger. Each clock cycle corresponds to one register.
    Resources This function requires FPGA resources proportional to the number of bits in x or y, whichever data type is larger.