Shifts x the number of bits specified by y.

The connector pane displays the default data types for this polymorphic function.


icon

Inputs/Outputs

  • ci16.png y —

    y can be any numeric representation. If y is greater than 0, the function shifts x left y bits (from least significant to most significant bit) and inserts zeros in the low-order bits. If y is less than 0, the function shifts x right y bits in the positive direction (from most significant to least significant bit) and inserts zeros in the high-order bits.

  • cu32.png x —

    x can be any integer representation. If x is an 8-, 16-, 32-, or 64-bit integer and y is greater than 8, 16, or 32, or 64 or is less than –8, –16, –32, or –64, respectively, the output value is all zeros.

  • iu32.png x << y —

    x << y is the result of the shift and has the same numeric representation as x.

    • FPGA Module Details

    The following details apply when you use this object in an FPGA VI.

    Note The following details are subject to change with each version of the LabVIEW FPGA Module.
    Single-Cycle Timed Loop Supported.
    Usage The logical shift operation shifts all bits including the sign bit of a signed integer. To preserve the sign of a signed integer, use the Scale By Power Of 2 function.
    Timing

    Inside single-cycle Timed Loop--When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x.

    Outside single-cycle Timed Loop--When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register.
    Resources This function requires FPGA resources proportional to the number of bits in x.