Returns the absolute value of the input.

The connector pane displays the default data types for this polymorphic function.


icon

Inputs/Outputs

  • cdbl.png x —

    x can be a scalar number, a fixed-point number, an array or cluster of numbers, an array of clusters of numbers, and so on.

    x cannot be an unsigned integer, because unsigned integers represent only non-negative integers.

  • idbl.png abs(x) —

    abs(x) is the absolute value of x.

    When x is of the form x = a + bi, that is, when x is complex, the following equation defines abs(x):

    • When you wire matrix data as an input to this function, a VI that includes subVIs that work with the matrix data type replaces the function. The resulting VI has the same icon but contains a matrix-specific algorithm. The node remains a VI if you disconnect the matrix from the inputs. Wire other data types as inputs to restore the original function. If you wire a data type to a function and that data type causes a basic math operation to fail, the function returns a NaN.

    If the absolute value of x is outside the range of the data type of x, abs(x) overflows to a value within the range of the data type. For example, if x is an 8-bit integer and the value of x is -128, abs(x) returns -128 since 128 is outside the range of 8-bit integers, -128 to 127.

    FPGA Module Details

    The following details apply when you use this object in an FPGA VI.

    Note The following details are subject to change with each version of the LabVIEW FPGA Module.
    Single-Cycle Timed Loop Supported.
    Usage If you use this function with the single-precision floating-point data type, refer to the Using the Single-Precision Floating-Point Data Type and Deciding Which Data Type to Use in FPGA Designs topics for resource use, latency, and single-cycle Timed Loop support implications.
    Timing

    Inside single-cycle Timed Loop--When you use this function inside a single-cycle Timed Loop, the combinatorial logic delay is proportional to the number of bits in x.

    Outside single-cycle Timed Loop--When you use this function outside a single-cycle Timed Loop, it takes one clock cycle and uses one register.

    If you use this function with the fixed-point data type, the overflow and rounding modes might impact timing.

    Resources This function requires FPGA resources proportional to the number of bits in x. If you use this function with the fixed-point data type, the overflow and rounding modes might impact resources.

    Examples

    Refer to the following example files included with LabVIEW.

    • labview\examples\Numerics\Numeric Functions.vi