Open LVDS Display Interface (OLDI) is a specification that defines a standard digital interface between a display source and a display device.

OLDI serializes parallel pixel data, synchronization signals, and control signals for transmission over LVDS differential pairs. OLDI minimizes wire count and electromagnetic emissions while preserving fully digital image quality. The specification draws upon LVDS (ANSI/TIA/EIA-644) as its physical layer. OLDI replaces the analog video interface between display controllers and flat panel LCD displays.
Note The Open LVDS Display Interface specification is also known as OpenLDI.

Physical Layer

OLDI uses Low Voltage Differential Signaling (LVDS) as defined in ANSI/TIA/EIA-644. OLDI serializes pixel data at a bit rate seven times the pixel clock (7:1 serialization ratio).

The interface uses up to 8 serial data lines (A0–A7) and up to 2 dedicated clock lines (CLK1 and CLK2). The number of active data lines depends on the pixel format in use:

Table 21. DSI-2 Physical Layer Options
Pixel Format Active Data Lines Clock Lines
18-bit Single Pixel A0–A2 CLK1
24-bit Single Pixel A0–A3 CLK1
18-bit Dual Pixel A0–A2, A4–A6 CLK1, CLK2
24-bit Dual Pixel A0–A7 CLK1, CLK2

Pixel Formats

Table 22. Pixel Formats
Pixel Format Description Color Depth
18-bit Single Pixel One pixel per cycle. 6 bits each for R, G, B 262,144 colors
24-bit Single Pixel One pixel per cycle. 8 bits each for R, G, B 16,777,216 colors
18-bit Dual Pixel Two pixels per cycle (upper and lower halves). 6 bits per channel 262,144 colors per pixel
24-bit Dual Pixel Two pixels per cycle (upper and lower halves). 8 bits per channel 16,777,216 colors per pixel

Dual dual pixel mode divides the display into an upper half and a lower half. One pixel for each half transmits simultaneously, with both halves synchronized horizontally and vertically.

Operating Modes

  • Unbalanced Mode: Transmits pixel data and control signals directly without modification. There is no mechanism to control the DC bias accumulation on signal lines over time.
  • Balanced (DC Balanced) Mode: Each data line transmits an additional DC Balance bit (DCBAL) per cycle alongside the 6-bit pixel data. The DCBAL bit tells the system to send the pixel data word either as is or inverted. The bit bases this choice on a running disparity calculation that reduces long‑term DC bias on each signal line. Balanced (DC Balanced) Mode sends control signals (HSYNC, VSYNC) unmodified using fixed DC-balanced code words. The Data Enable (DE) signal multiplexes onto the CLK1 and CLK2 signal lines instead of occupying a dedicated data lane slot.

Control Signals

OLDI includes the following control signals in the serialized data stream.
  • HSYNC - Horizontal synchronization. HSYNC marks the end of each scan line.
  • VSYNC - Vertical synchronization. VSYNC marks the end of each frame.
  • DE - Data Enable. DE delineates active pixel data from blanking intervals.
  • CNTLE / CNTLF - Implementation-specific control signals. CNTLE / CNTLF are available in dual pixel modes only.

Auxiliary Interface (DDC/EDID)

A separate bidirectional control channel uses the Display Data Channel (DDC) protocol (DDC2B, I²C-based) for display identification and configuration. The display device stores an Extended Display Identification Data (EDID) structure. The display source reads the EDID structure to determine supported display resolutions, pixel formats, and timing modes.

Transmission Direction

OLDI is unidirectional. Pixel data and control signals flow from the display source (transmitter) to the display device (receiver). The DDC/EDID control channel is bidirectional and operates on a separate interface.

Support in FlexRIO Interface Adapter Modules

The FPGA on the carrier module interfaces to SerDes components and implements a subset of the OLDI protocol.

  • Physical Layer - Interface adapter modules support LVDS.
Table 23. Supported Pixel Formats
Pixel Format Support
18-bit Single Pixel Not supported
24-bit Single Pixel Supported
18-bit Dual Pixel Not supported
24-bit Dual Pixel Supported. The two pixel streams are received independently. You must re-combined the pixel streams.

  • Operating Mode - Interface adapter modules only support Unbalanced Mode. Interface adapter modules do not support Balanced (DC Balanced) Mode.

  • Transmission Direction - Interface adapter modules only support the receive (display device). Interface adapter modules do not support Transmit (display source).

  • Data Logging Format - OLDI logs received data in DSI-2 RGB-8-8-8 packet format.