Display Serial Interface 2 (DSI-2) is a MIPI Alliance specification defining a high-speed serial interface between a host processor and a peripheral device. The peripheral device is typically a display module. DSI-2 serializes pixel data, commands, and control signals that are traditionally carried on a parallel bus.

Physical Layers

DSI-2 supports three physical layer options.
Table 18. DSI-2 Physical Layer Options
Physical Layer PHY Wires per Lane Lane Count
D Option D-PHY v3.0/3.5 2-wire differential 1 to 4 data lanes plus optional forwarded clock lane
D Option (ECM) D-PHY v3.5 2-wire differential 1 to 4 data lanes, clock embedded in data
C Option C-PHY v2.1 3-wire 1 to 4 lanes, clock embedded per-lane
  • The D Option uses a dedicated forwarded clock lane, or embedded clock in ECM mode, and 2-wire differential data lanes.
  • The C Option option uses 3-wire lanes with an embedded per-lane clock. The C Option distributes data in 2-byte (16-bit) units, converting every 2 bytes into 7 symbol transitions.
  • The C option uses 3‑wire lanes with an embedded per‑lane clock. The C Option distributes data in 2‑byte (16‑bit) units and converts every 2 bytes into 7 symbol transitions.

Operating Modes

  • Command Mode—Used with display modules that have an internal display controller and frame buffer. The host sends commands, parameters, and pixel data to the display controller. The display manages its own refresh. Requires a bidirectional interface. Data Lane 0 must support both transmit and receive directions. Communication in the reverse direction (peripheral to host) uses Low Power (LP) mode only.
  • Video Mode—Used with display modules that have no internal frame buffer. The host streams a continuous pixel feed. Transmits pixel data in High Speed (HS) mode. Supports three sub-modes of transmission.
    • Non-Burst with Sync Pulses: sync start packets and sync end packets delimit the active region.
    • Non-Burst with Sync Events: single sync event packets mark timing boundaries.
    • Burst Mode: transmits pixel data as fast as possible. Uses blanking intervals for low-power periods.
    Video mode might be unidirectional where no reverse-direction capability is required.

    • Key Protocol Concepts

    • Packets: The fundamental data unit. Each packet has a header with a Data Identifier (DI) byte, a Word Count or data fields, and an Error-Correcting Code (ECC). Long packets additionally include a payload and a CRC checksum.
    • Virtual Channels: Up to 4 virtual channels allow traffic for multiple peripherals to share one DSI link.
    • Lane Scalability: 1–4 data lanes. Additional lanes increase bandwidth by distributing bytes (D option) or byte pairs (C option) across the lanes.
    • ECC: A modified Hamming code protects packet headers. ECC provides single-bit error correction and 2-bit error detection.
    • Data Scrambling: Optional PRBS-based per-lane scrambling reduces EMI.
    • Latency Reduction and Transport Efficiency (LRTE): Optional feature. LRTE reduces inter-packet latency by using efficient packet delimiters (EPD) to avoid Low Power State transitions between packets.
    • Display Stream Compression (DSC/VDC-M): Supports compressed pixel streams to reduce bandwidth requirements.

    Transmission Direction

    Table 19. Transmission Direction
    Direction Mode Lane
    Host to Peripheral (Forward) HS or LP All data lanes
    Peripheral to Host (Reverse) LP only Data Lane 0 only

    A Bus Turn-Around (BTA) token-passing mechanism manages changes in the bus direction.

    Support in FlexRIO Interface Adapter Modules

    The FPGA on the carrier module interfaces to SerDes components and implements a subset of the DSI-2 protocol.
    • Physical Layer- Interface adapter modules only support the D Option (D-PHY) physical layer. Interface adapter modules do not support C-PHY physical layer.
    • Operating Mode- Interface adapter modules only support Video Mode. Video Mode is unidirectional. Interface adapter modules do not support Command Mode.
    Table 20. Video Mode Transmission Sub-Modes
    Sub-Mode Support
    Non-Burst with Sync Pulses Fully supported
    Non-Burst with Sync Events Supported for transmit and receive. This sub-mode requires the display to be disabled in current example code.
    Burst Mode Not supported
    • Supported Image Data Formats- Interface adapter modules only support the RGB888 (24-bit RGB) pixel format.
    • Lane Behavior- The interface transitions to Low Power (LP) mode between packets. Each High Speed (HS) transmission consists of a single packet. Interface adapter modules do not support continuous HS mode spanning multiple packets.