Camera Serial Interface 2 (CSI-2) is a MIPI Alliance specification defining a standard high-speed serial interface between a camera (transmitter) and a host processor (receiver). CSI-2 serializes image data, control signals, and embedded metadata that traditionally require many parallel interconnects.

Physical Layers

CSI-2 supports two high-speed physical layer options.
Table 16. CSI-2 Physical Layer Options
Physical Layer PHY Wires per Lne Lane Count Clock
D-PHY FCM D-PHY v3.6 2-wire differential 1–N data lanes plus one clock lane Forwarded clock lane
D-PHY ECM D-PHY v3.6 2-wire differential 1–N data lanes Clock embedded in data
C-PHY C-PHY v3.0 3-wire 1–N lanes Clock embedded per lane
  • The D-PHY option provides a unidirectional high‑speed link. Forwarded Clock Mode (FCM), D‑PHY uses a dedicated 2‑wire clock lane alongside the data lanes. In Embedded Clock Mode (ECM), D‑PHY recovers the clock from the data lanes. in ECM, D-PHY also eliminates the separate clock lane.
  • The C-PHY option uses 3-wire lanes with an embedded per-lane clock. C-PHY operates in either 6-Wirestate Mode or 18-Wirestate Mode. The C-PHY option distributes data in 16-bit or 32-bit units respectively.

Command and Control Interface

A separate bidirectional control interface is used for camera configuration and register access. This interface is compatible with I²C and I3C SDR/DDR.
  • I2C is a standard two-wire serial control bus.
  • I3C SDR/DDR is an improved inter-integrated circuit bus that supports higher speeds and additional features.

With CSI-2 version 3.0, you can use Lane 1 of a D-PHY or C-PHY link as a bidirectional Unified Serial Link (USL). The bidirectional link enables the CCI function over the same physical data link without a separate control bus.

Key Protocol Concepts

  • Packets: The fundamental data unit. Packets are either Long Packets or Short Packets. Long packets include a header, payload, and 16-bit CRC checksum. Short packets only include a header that is used for synchronization. The packet header contains a Data Identifier (DI) byte and a Word Count (WC) or data field. An ECC protects the Word Count.
  • Virtual Channels: You can multiplex up to 32 independent data streams (virtual channels) over a single CSI-2 link. A Virtual Channel Identifier (VCI) in the packet header identifies each stream.
  • Lane Scalability: Multiple data lanes increase bandwidth. The transmitter distributes bytes (D-PHY) or byte pairs (C-PHY) across lanes. The receiver merges the bytes or byte pairs back.
  • ECC: A modified Hamming code protects packet headers. ECC provides single-bit error correction and 2-bit error detection.
  • Data Scrambling: Optional PRBS-based per-lane scrambling reduces EMI.
  • Latency Reduction and Transport Efficiency (LRTE): An optional feature that reduces inter-packet latency by using efficient packet delimiters (EPD) to avoid Low Power State transitions between packets.
  • Data Compression: Supports RAW data compression (10→8, 10→7, 10→6, 12→10, 12→8, 12→7, 12→6 bit schemes) and Multi-Pixel Compression (MPC) for these image sensors.
    • Bayer image sensors
    • Tetra-Cell image sensors
    • Nona-Cell image sensors

Frame and Packet Structure

CSI-2 uses synchronization short packets to delimit frames and lines.

  • Frame Start (FS): Marks the beginning of a frame
  • Frame End (FE): Marks the end of a frame
  • Line Start (LS): Marks the beginning of a line (optional)
  • Line End (LE): Marks the end of a line (optional)

Supported Image Data Formats

CSI-2 supports a wide range of image data formats.
  • RAW: RAW6, RAW7, RAW8, RAW10, RAW12, RAW14, RAW16, RAW20, RAW24, RAW28
  • RGB: RGB444, RGB555, RGB565, RGB666, RGB888
  • YUV: YUV420 8-bit (Legacy), YUV420 8-bit, YUV420 10-bit, YUV422 8-bit, YUV422 10-bit
  • Generic: Null, Blanking, Embedded data, User-defined 8-bit (4 types)
  • Compressed: JPEG8, Display Stream Compression (DSC)

Transmission Direction

CSI-2 is primarily unidirectional. Image data flows from transmitter (camera) to receiver (host processor). The CCI control interface is bidirectional, operating separately over I²C/I3C or over USL on Lane 1.

Support in FlexRIO Interface Adapter Modules

The FPGA on the carrier module interfaces to SerDes components and implements a subset of the CSI-2 protocol.

  • Physical Layer—Interface adapter modules only support the D-PHY physical layer. Interface adapter modules do not support C-PHY physical layer.
    • Table 17. Supported Features
    Feature Support
    D-PHY Forwarded Clock Mode (FCM) Supported
    CCI (Command and Control Interface) I²C supported
    Virtual Channels Supported
    • Supported Image Data Formats: All CSI-2 image data formats are supported for transmit and receive. Note that the utility for generating TDMS files with a ramp pattern is limited to RAW data formats.
    • Lane Behavior: The interface transitions to Low Power (LP) state between packets. This state is standard behavior without LRTE.