This asynchronous node adopts a VI and, during execution, transfers data between the asynchronous wires and the adopted VI. To use the harness node, drag and drop a dataflow VI onto the harness node. After you drop the VI onto the harness node, the harness node displays the adopted VI in the center and creates asynchronous wire terminals for the input and output data. The harness node creates default data exchange policies for the asynchronous output wires. To change the data exchange policy for an output wire, click the data exchange policy glyph for that wire. Double-clicking the harness node opens the adopted VI.

If the boundary of the harness node is a thin line, it indicates that you have made one or more configuration changes that will be lost if you drop another VI into the harness. Dropping the same VI onto the harness node also erases these configuration changes. The harness boundary changes to a thick line to indicate that no changes have been made that would be lost if you dropped another VI onto the harness.
Note The harness node does not support adopting a VI that has array output parameters. If the adopted VI has array input parameters, a dataflow wire must be used for those parameters. Express VIs and VIs from the FPGA Math and Analysis palette must be placed on the LabVIEW block diagram and configured prior to being dragged onto the harness node. After you place one of these VIs in the harness node, double-clicking the harness node does not open the VI configuration page.

Harness Node Details

Click the glyph representing the data exchange policy for the wire (, , or ) to configure the data exchange policy and buffer depth.

The default behavior of the harness node with respect to FIFO reads and writes is as follows:

  • When an input FIFO is empty, the harness node does not execute the adopted VI until a sample is read from all input FIFOs present.
  • When an output FIFO is full, the harness node does not read any inputs or execute the adopted VI until all the writes succeed.
  • If any of the handshaking terminals are present on the adopted VI, this behavior is modified. Refer to the Handshaking Signal Protocol section for more information about this behavior.
Select Loop Type from the shortcut menu to configure the execution mode of the adopted VI. The harness node can adopt the VI in a while loop (indicated by a gray border around the adopted VI region) or a single-cycle timed loop (indicated by a light blue border around the adopted VI region). If you select the single-cycle timed loop, the clock domain is configurable. You can use the top-level clock or expose a clock terminal. If you choose the latter, wire a base or derived clock from one of the other nodes on this palette.
Tip Because the harness creates the loop for you, there is no loop in the diagram of the VI you embed in the timed loop node. To maintain the state of the adopted VI, the use of feedback node is recommended.

The harness node stores a relative path to an adopted VI. This path is relative to the path of the FPGA VI that contains the harness node. You must save the FPGA VI that contains the harness node before the harness node can adopt a VI. As long as the FPGA VI that contains the harness node maintains the same relative location to the adopted VI within the harness, the harness node is always in a valid state.

Handshaking Signal Protocol

The harness node supports the handshaking signal protocol used by some of the LabVIEW FPGA Math and Analysis Express VIs. This protocol enables these Express VIs to maximize their throughput by executing every cycle of a single-cycle timed loop. These handshaking signals may also be employed by your adopted VI and may be used in a normal loop as well. If the adopted VI supports this protocol, the harness node recognizes the presence of the terminals and generates the appropriate code. These handshaking signal terminals are entirely optional. If the harness node detects the presence of these signals, their acronyms appear at the bottom of the node, though the terminals themselves are not exposed by the harness.

Handshaking signal terminals must adhere to the following naming scheme.

  • Input valid—Boolean input signal that is set to TRUE when the data input to the VI is valid.
  • Ready for input—Boolean output signal that is set to TRUE when the VI can accept new data on the next iteration.
  • Output valid—Boolean output signal that is set to TRUE when the data generated by the VI is valid.
  • Ready for output—Boolean input signal that, when TRUE, instructs the VI to write data into its outputs, if it can. When FALSE, this signal inhibits data generation by the VI.

    • The harness node reads the input FIFO wires only when the value of ready for input was TRUE on the previous iteration. The harness node uses a value of TRUE for ready for input when it first begins execution.

    If an input FIFO is empty, the harness node executes the VI with the value of the input valid control set to FALSE. If there are multiple input FIFOs, input valid is set to TRUE only when data is successfully read from all buffers.

    If the output valid indicator is FALSE, no data is written to the output FIFOs or circular buffers. If output valid is TRUE but an output FIFO is full, the VI is executed on the next iteration with its ready for output control set to FALSE. The data from the failed write is stored by the harness node for further write attempts. The ready for output control is not set to TRUE again until all the FIFO writes succeed.