This node reads I/Q data from an ADC and writes it into an asynchronous wire. The name of the associated ADC is shown on the node.

  • I/Q Clock supplies the ADC I/Q clock to the asynchronous timing wire. The ADC I/Q Clock is the clock domain in which data is written to the output FIFO at the I/Q Data terminal. The name of this terminal varies.
  • I/Q Data supplies the data to an asynchronous wire configured for the FIFO data exchange policy. The name of this terminal varies.An I/Q data pair is always packed into a single unsigned 32-bit word with the I data in the upper 16 bits and the Q data in the lower 16 bits. Click the FIFO icon () to configure the depth of the buffer. Supported Data Exchange Policy: FIFO,
  • Start Trigger supplies a start trigger to the ADC node. The ADC is configured by a host program, so the ADC cannot start running before that configuration is complete. Click the polarity indicator () to toggle whether the ADC node detects a rising edge trigger (shown) or a falling edge trigger.
  • Overflow returns whether the ADC failed to write data because the output FIFO is full. A TRUE is written if the write fails, and this data is lost.

User-Enabled Terminals

This node has several terminals you can enable by selecting options from the node shortcut menu.

Stop Condition — Right-click the node and select Stop Condition»Sample Count or Stop Condition»Trigger Edge to create one of the following two terminals:

  •   Stop Condition»Sample Count specifies the number of samples to acquire before stopping the ADC and waiting for another start trigger.
  •   Stop Condition»Trigger Edge supplies a digital edge stop trigger to the ADC node. Click the polarity indicator () to toggle whether the ADC node detects a rising edge trigger (shown) or a falling edge trigger.

ADC Node Details

When you drop the ADC node on the LabVIEW block diagram, it is automatically configured for ADC 0. To select ADC 1, right-click the node and select ADC 1 from the shortcut menu.