SRAM

The PXIe-5624 has one bank of static random-access memory (SRAM), which is accessible from the FPGA. The PXIe-5624 supports SRAM access through socketed component-level IP (CLIP).

Refer to the PXIe-5624 Specifications for information about the SRAM size and throughput.

Configuring SRAM with Socketed CLIP

Use the socketed CLIP interface to communicate directly with the onboard SRAM. The socketed CLIP lists all memory interfaces that are compatible with the SRAM. The SRAM CLIP is present in the LabVIEW project by default but is disabled.

Complete the following steps to configure SRAM with socketed CLIP.
  1. Right-click the SRAM CLIP and select Properties from the shortcut menu to display the SRAM Properties dialog box.
  2. Select Enable Memory to display the SRAM configuration options.
  3. Select the appropriate clock for your project under Clock Selections. You can use the SRAM CLIP in any single clock domain. You can select only clocks already added to the project.

SRAM Properties Dialog Box

Right-click SRAM Bank in Project Explorer and select Properties from the shortcut menu to display the SRAM Properties dialog box. Select the Enable SRAM checkbox to display the General and Clock Selections pages in the Category list.

General Page

Use this page to configure the type of memory interface that should be used when communicating with external SRAM.

This page contains the following components:

  • Enable Memory—Enables the SRAM. Unchecking this box disables access to the SRAM.
  • Memory Interface—Lists all memory interfaces that are compatible with the SRAM. If multiple versions of a memory interface are available, the version information displays next to the memory interface name.
  • Details—Displays general information about the SRAM memory interface.
  • Path—Displays the file system path to the XML file for the currently selected memory interface file.
  • Reload—Reloads the currently selected memory interface in the table. Use the Reload button if you modify a memory interface XML file on disk after you configure it for use with your FPGA target. Reload updates the I/O in the LabVIEW project and details information, but changes may not be visible in the Memory Interface or Path dialog boxes.

    • The PXIe-5624 ships with one memory interface support option, which provides access to the external SRAM memory.

    Clock Selections Page

    Use this page to link each clock port defined by the CLIP to a clock on the FPGA target. You must add the FPGA clock to the LabVIEW project before you can link to the FPGA clock. You can also use the Create Necessary Clocks button to generate a clock at the frequency you specify, using one of the available clocks in the Connection drop-down menu.