• Read or Write Device Register—Reads or writes registers in the fixed portion of the FPGA, which is not visible on the VI. Unlike most I/O methods, this method is associated with the IF digitizer target in general, and not with any specific I/O resource.
  • Fixed Logic RegPort Interface—Reserved for NI use. Use this I/O method only with IP provided by NI.
  • Wait on Any Edge—Pauses the execution of the I/O Method Node until the next falling or rising edge of the digital signal. The Timeout input on this method specifies the number of FPGA clock cycles that the Wait on Any Edge method waits for the next falling or rising edge.
    • 0 = Causes the method to timeout immediately.
    • Negative value = Causes the method to wait indefinitely.
    • Positive value = Causes the method to wait for that number of clock cycles before timing out.
  • Wait on Falling Edge—Pauses the execution of the I/O Method Node until the next falling edge of the digital signal. The Timeout input on this method specifies the number of FPGA clock cycles that the Wait on Falling Edge method waits for the next falling edge.
    • 0 = Causes the method to timeout immediately.
    • Negative value = Causes the method to wait indefinitely.
    • Positive value = Causes the method to wait for that number of clock cycles before timing out.
  • Wait on High Level—Pauses the execution of the I/O Method Node until the digital signal is high. The Timeout input on this method specifies the number of FPGA clock cycles that the Wait on High Level method waits for the next logic high level.
    • 0 = Causes the method to timeout immediately.
    • Negative value = Causes the method to wait indefinitely.
    • Positive value = Causes the method to wait for that number of clock cycles before timing out.
  • Wait on Low Level—Pauses the execution of the I/O Method Node until the digital signal is low. The Timeout input on this method specifies the number of FPGA clock cycles that the Wait on Low Level method waits for the next logic low level.
    • 0 = Causes the method to timeout immediately.
    • Negative value = Causes the method to wait indefinitely.
    • Positive value = Causes the method to wait for that number of clock cycles before timing out.
  • Wait on Rising Edge—Pauses the execution of the I/O Method Node until the next rising edge of the digital signal. The Timeout input on this method specifies the number of FPGA clock cycles that the Wait on Rising Edge method waits for the next rising edge.
    • 0 = Causes the method to timeout immediately.
    • Negative value = Causes the method to wait indefinitely.
    • Positive value = Causes the method to wait for that number of clock cycles before timing out.
  • Set Output Data—Writes data to the digital line or port without enabling the line or port. You can use the Set Output Data method to optimize performance when performing successive writes to a DIO resource.
  • Set Output Enable—Determines whether the digital input and output resource reads external input or writes output. Wiring TRUE to Set Output Enable for a digital line allows the resource to write data. Wiring FALSE to Set Output Enable allows the resource to read external data.